MC54/74HC589

High–Speed CMOS Logic Data

DL129 — Rev 6

3–3

MOTOROLA

Symbol

Parameter

VCC

V

Guaranteed Limit

Unit

Symbol

Parameter

VCC

V

– 55 to

25

_C

v 85_C

v 125_C

Unit

fmax

Maximum Clock Frequency (50% Duty Cycle)

(Figures 2 and 8)

2.0

4.5

6.0

6.0

30

35

4.8

24

28

4.0

20

24

MHz

tPLH,

tPHL

Maximum Propagation Delay, Latch Clock to QH

(Figures 1 and 8)

2.0

4.5

6.0

210

42

36

265

53

45

315

63

54

ns

tPLH,

tPHL

Maximum Propagation Delay, Shift Clock to QH

(Figures 2 and 8)

2.0

4.5

6.0

175

35

30

220

44

37

265

53

45

ns

tPLH,

tPHL

Maximum Propagation Delay, Serial Shift/Parallel Load to QH

(Figures 4 and 8)

2.0

4.5

6.0

175

35

30

220

44

37

265

53

45

ns

tPLZ,

tPHZ

Maximum Propagation Delay, Output Enable to QH

(Figures 3 and 9)

2.0

4.5

6.0

150

30

26

190

38

33

225

45

38

ns

tPZL,

tPZH

Maximum Propagation Delay, Output Enable to QH

(Figures 3 and 9)

2.0

4.5

6.0

150

30

26

190

38

33

225

45

38

ns

tTLH,

tTHL

Maximum Output Transition Time, Any Output

(Figures 1 and 8)

2.0

4.5

6.0

60

12

10

75

15

13

90

18

15

ns

Cin

Maximum Input Capacitance

—

10

10

10

pF

Cout

Maximum Three–State Output Capacitance (Output in

High–Impedance State)

—

15

15

15

pF

NOTES:

1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

CPD

Power Dissipation Capacitance (Per Package)*

Typical @ 25

°C, VCC = 5.0 V

pF

CPD

Power Dissipation Capacitance (Per Package)*

50

pF

* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the

Motorola High–Speed CMOS Data Book (DL129/D).