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DA28F320J5A-120 Datasheet(PDF) 1 Page - Intel Corporation |
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DA28F320J5A-120 Datasheet(HTML) 1 Page - Intel Corporation |
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1 / 51 page  5 Volt Intel StrataFlash® Memory 28F320J5 and 28F640J5 (x8/x16) Datasheet Product Features Capitalizing on two-bit-per-cell technology, 5 Volt Intel StrataFlash® memory products provide 2Xthe bits in 1Xthe space. Offered in 64-Mbit (8-Mbyte) and 32-Mbit (4-Mbyte) densities, Intel StrataFlash memory devices are the first to bring reliable, two-bit-per-cell storage technology to the flash market. Intel StrataFlash memory benefits include: more density in less space, lowest cost-per-bit NOR devices, support for code and data storage, and easy migration to future devices. Using the same NOR-based ETOX™ technology as Intel’s one-bit-per-cell products, Intel StrataFlash memory devices take advantage of 400 million units of manufacturing experience since 1988. As a result, Intel StrataFlash components are ideal for code or data applications where high density and low cost are required. Examples include networking, telecommunications, audio recording, and digital imaging. Intel StrataFlash memory components deliver a new generation of forward-compatible software support. By using the Common Flash Interface (CFI) and the Scalable Command Set (SCS), customers can take advantage of density upgrades and optimized write capabilities of future Intel StrataFlash memory devices. Manufactured on Intel’s 0.4 micron ETOX™ V process technology and Intel’s 0.25 micron ETOX VI process technology, 5 Volt Intel StrataFlash memory provides the highest levels of quality and reliability. s High-Density Symmetrically-Blocked Architecture — 64 128-Kbyte Erase Blocks (64 M) — 32 128-Kbyte Erase Blocks (32 M) s 4.5 V–5.5 V VCC Operation — 2.7 V–3.6 V and 4.5 V–5.5 V I/O Capable s 120 ns Read Access Time (32 M) 150 ns Read Access Time (64 M) s Enhanced Data Protection Features — Absolute Protection with VPEN =GND — Flexible Block Locking — Block Erase/Program Lockout during Power Transitions s Industry-Standard Packaging — SSOP Package (32, 64 M) TSOP Package (32 M) s Cross-Compatible Command Support — Intel Basic Command Set — Common Flash Interface — Scalable Command Set s 32-Byte Write Buffer — 6 µ s per Byte Effective Programming Time s 6,400,000 Total Erase Cycles (64 M) 3,200,000 Total Erase Cycles (32 M) — 100,000 Erase Cycles per Block s Automation Suspend Options — Block Erase Suspend to Read — Block Erase Suspend to Program s System Performance Enhancements —STS Status Output s Operating Temperature –20 °C to + 85 °C (–40 °C to +85°Con.25 micron ETOXVI) process technology parts) Order Number: 290606-015 April 2002 Notice: This document contains information on products in production. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizinga design. |
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