10

8535B–SEEPR–7/08

AT25320B/640B

A write instruction requires the following sequence. After the CS line is pulled low to select the

is brought high. The low-to-high transition of the CS pin must occur during the SCK low-time

immediately after clocking in the D0 (LSB) data bit.

The READY/BUSY status of the device can be determined by initiating a read status register

(RDSR) instruction. If Bit 0 = “1”, the write cycle is still in progress. If Bit 0 = “0”, the write cycle

has ended. Only the RDSR instruction is enabled during the write programming cycle.

The AT25320B/640B is capable of a 32-byte page write operation. After each byte of data is

received, the five low-order address bits are internally incremented by one; the high-order bits of

the address will remain constant. If more than 32 bytes of data are transmitted, the address

counter will roll over and the previously written data will be overwritten. The AT25320B/640B is

automatically returned to the write disable state at the completion of a write cycle.

NOTE: If the device is not write-enabled (WREN), the device will ignore the write instruction and

will return to the standby state, when CS is brought high. A new CS falling edge is required to

reinitiate the serial communication.

3.

Timing Diagrams

Figure 3-1.

Synchronous Data Timing (for Mode 0)

Table 2-6.

Address Key

Address

AT25320B

AT25640B

A

N

A

A

Don’t Care Bits

SO

V

OH

V

OL

HI-Z

HI-Z

t

V

VALID IN

SI

V

IH

V

IL

t

H

t

SU

t

DIS

SCK

V

IH

V

IL

t

WH

t

CSH

CS

V

IH

V

IL

t

CSS

t

CS

t

WL

t

HO