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AT25320B-TH-T Datasheet(PDF) 9 Page - ATMEL Corporation |
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AT25320B-TH-T Datasheet(HTML) 9 Page - ATMEL Corporation |
9 / 23 page 9 8535B–SEEPR–7/08 AT25320B/640B The WRSR instruction also allows the user to enable or disable the write protect (WP) pin through the use of the Write Protect Enable (WPEN) bit. Hardware write protection is enabled when the WP pin is low and the WPEN bit is “1”. Hardware write protection is disabled when either the WP pin is high or the WPEN bit is “0”. When the device is hardware write protected, writes to the status register, including the block protect bits and the WPEN bit, and the block-pro- tected sections in the memory array are disabled. Writes are only allowed to sections of the memory that are not block-protected. NOTE: When the WPEN bit is hardware write protected, it cannot be changed back to “0” as long as the WP pin is held low. READ SEQUENCE (READ): Reading the AT25320B/640B via the Serial Output (SO) pin requires the following sequence. After the CS line is pulled low to select a device, the read op- code is transmitted via the SI line followed by the byte address to be read (A15–A0, see Table 2- 6). Upon completion, any data on the SI line will be ignored. The data (D7–D0) at the specified address is then shifted out onto the SO line. If only one byte is to be read, the CS line should be driven high after the data comes out. The read sequence can be continued since the byte address is automatically incremented and data will continue to be shifted out. When the highest address is reached, the address counter will roll over to the lowest address allowing the entire memory to be read in one continuous read cycle. WRITE SEQUENCE (WRITE): In order to program the AT25320B/640B, two separate instruc- tions must be executed. First, the device must be write enabled via the WREN instruction. Then a write (WRITE) instruction may be executed. Also, the address of the memory location(s) to be programmed must be outside the protected address field location selected by the block write protection level. During an internal write cycle, all commands will be ignored except the RDSR instruction. Table 2-4. Block Write Protect Bits Level Status Register Bits Array Addresses Protected BP1 BP0 AT25320B AT25640B 0 0 0 None None 1(1/4) 0 1 0C00 −0FFF 1800 −1FFF 2(1/2) 1 0 0800 −0FFF 1000 −1FFF 3(All) 1 1 0000 −0FFF 0000 −1FFF Table 2-5. WPEN Operation WPEN WP WEN Protected Blocks Unprotected Blocks Status Register 0 X 0 Protected Protected Protected 0 X 1 Protected Writeable Writeable 1 Low 0 Protected Protected Protected 1 Low 1 Protected Writeable Protected X High 0 Protected Protected Protected X High 1 Protected Writeable Writeable |
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