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FEATURES

TUSB6020

USB 2.0 HIGH-SPEED ON-THE-GO DUAL-ROLE CONTROLLER

SCPS170E – JANUARY 2007 – REVISED MARCH 2008

www.ti.com

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• USB On-the-Go (OTG) Controller Core

• Integrated USB 2.0 OTG PHY

–

Uses Mentor Graphics USB 2.0 OTG Core

–

Fully Compliant with USB 2.0 Standard and

USB 2.0 Transceiver Macrocell Interface

–

Dual-Role Controller Can Operate Either as

(UTMI) Revision 1.05

a Function Controller for a USB Peripheral

or as the Host/Peripheral in Point-to-Point

–

Optimized One-Port Operation at Low

or Multipoint Communications With Other

Speed (1.5 Mbps), Full Speed (12 Mbps),

USB Functions

and High Speed (480 Mbps)

–

Compliant With the USB 2.0 Standard for

–

Supports UTMI+3 Level 3 (Host and OTG

High-Speed (480-Mbps) Functions and With

Devices, High/Full/Low Speed and

OTG Supplement to USB 2.0 Specification

Preamble Packet)

–

Supports OTG Communications With One

–

Protection Circuitry to Withstand Possible

or More High-, Full-, or Low-Speed Devices

VBUS Short

–

Supports Session Request Protocol (SRP)

–

Use 19.200-MHz or 24.000-MHz Reference

and Host Negotiation Protocol (HNP)

Clock Input as a Crystal or External Clock

Driver

–

Supports Suspend-and-Resume Signaling

–

At-Speed Built-In Self Test (BIST) With

–

Configurable for up to 4 Transmit

Internal Asynchronous Capability Through

Endpoints or up to 4 Receive Endpoints

Loopback

–

Configurable FIFOs, Including the Option of

–

On-Chip Integrated Accurate 45-

Ω

Dynamic FIFO Sizing

High-Speed Termination, 1.5-k

Ω Pullup, and

–

16k-Byte RAM for USB Endpoint FIFO

15-k

Ω Pulldown Resistors

Shared by USB In/Out Endpoints

–

On-Chip Phase-Locked Loop (PLL) to

–

Support for External Direct Memory Access

Reduce Noise on High-Speed Clocks

(DMA) to FIFOs

–

Active Power Consumption Less Than

–

Soft Connect/Disconnect Option

100 mW

–

Performs All Transaction Scheduling in

• VLYNQ 2.0 Interface to External Host

Hardware

Controller

• System Control Module

–

High-Speed (150-MHz) Point-to-Point Serial

–

Controls Clock and Reset Generation and

Interface for Direct Connection to Other

Distribution

VLYNQ Interface

–

Controls and Observes Device Power

–

Supports 4 Receive (RX) and 4 Transmit

States

(TX) Lines

–

Supports External Power Management

–

Memory-Mapped Master/Slave

–

Hardware Flow Control Internal Loopback

Mode

–

Multichannel DMA Controller

–

Integrated List Processor Capable of

Parsing Communications Port

Programming Interface (CPPI)

3.0-Compliant Buffer Descriptors

• High-Performance 80-Pin

MicroStar BGA™/MicroStar Junior™

ZQE Package

• High-Performance 80-Pin PFC Package

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

MicroStar BGA, MicroStar Junior are trademarks of Texas Instruments.

3

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Copyright © 2007–2008, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.