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7737B–AERO–05/08

AT7911E

In the protocol mode an additional FIFO (acknowledge FIFO) is used to decouple sending of

acknowledges from receiving new data when the transmit path is currently occupied by a run-

ning packet transmission.

4.1.1.3

Command Execution Unit

This unit performs activating resp. deactivating of the CPU reset and the specific external sig-

nals and provides the capability to reset one or all links inside the AT7911E, all actions

requested by the decoded commands from the protocol execution unit.

The unit contains a register controlling the enable/disable state of safety critical commands

which is set into the 'enable' state upon command request and which is reset after a safety criti-

cal command has been executed.

The CPU reset and the specific external signals are forwarded to the Protocol Command Inter-

face (PRCI).

4.2

Communication Memory Interface (COMI)

The COMI performs autonomous accesses to the communication memory of the module to store

data received via the links or to read data to be transmitted via the links. The COMI consists of

individual memory address generators for the receive and transmit direction of every SpaceWire

link channel. The access to the memory is controlled via an arbitration unit providing a fair arbi-

tration scheme. Two AT7911E can share one DPRAM without external arbitration logic.

The data bus width is scalable (8/16/32 bit) to allow flexible integration with any CPU type.

Operation in little or big endian mode is configurable through internal registers.

The COMI address bus is 16 bit wide allowing direct access of up to 64K words (32 bits) of the

DPRAM. Two chip select signals are provided to allow splitting of the 64k address space in two

memory banks.

4.3

Host Control Interface (HOCI)

The HOCI gives read and write access to the AT7911E configuration registers and to the

SpaceWire channels for the controlling CPU. Viewed from the CPU, the interface behaves like a

peripheral that generates acknowledges to synchronize the data transfers and which is located

somewhere in the CPU's address space.

Packets can be transmitted or received directly via the HOCI. In this case the Communication

Memory (DPRAM) is not strictly needed. However, in this case the packet size should be limited

to avoid frequent CPU interaction.

The data bus width is scalable (8/16/32 bit) to allow flexible integration with any CPU type. The

byte alignment can be configured for little or big endian mode through an external pin.

Additionally, the HOCI contains the interrupt signalling capability of the AT7911E by providing an

interrupt output, the interrupt status register and interrupt mask register to the local CPU.

A special pin is provided to select between control of the AT7911E by HOCI or by link. If control

by link is enabled, the host data bus functions as a 32-bit general purpose interface (GPIO).

4.4

Protocol Command Interface (PRCI)

The PRCI collects the decoded commands from all PPUs and forwards them to external circuitry

via 5 special pins.