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FMP3217BA0-FXXX Datasheet(PDF) 9 Page - FIDELIX |
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FMP3217BA0-FXXX Datasheet(HTML) 9 Page - FIDELIX |
9 / 10 page FMP3217BA0(7) CMOS LPRAM Revision 0.2 Feb. 2007 9 1. A write occurs during the overlap (tWP) of low /CS and /WE. A write begins when /CS goes low and /WE goes low with asserting /UB or /LB for single byte operation or simultaneously asserting /UB and /LB for double byte operation. A write ends at the earliest transition when /CS goes high and /WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the /CS going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high. 5. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 20us. WRITE CYCLE (4) (/UB, /LB controlled) Address /CS1 /UB, /LB /WE Data Out tWC tWR(4) tBW tWP(1) High-Z High-Z Data Valid tDW tDH Data in tCW(2) tAW tAS(3) CS2 1. A write occurs during the overlap (tWP) of low /CS and /WE. A write begins when /CS goes low and /WE goes low with asserting /UB or /LB for single byte operation or simultaneously asserting /UB and /LB for double byte operation. A write ends at the earliest transition when /CS goes high and /WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the /CS going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high. 5. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 20us. 6. In case page address is over 3ns, write to the invalid address can occur. PAGE WRITE CYCLE (Address controlled, CS2=VIH) A4~A20 /CS1 /UB, /LB /WE Data Out tAS(3) High-Z Data Undefined Data Valid tDW tOW tWHZ Data in A0~A3 tWC tPC tPC tPC tPC tPC tPC tPC High-Z tDH Data Valid tDH tDW tDH tDW tDH tDW tDH tDW tDH tDW tDH tDW tDH tDW Data Valid Data Valid Data Valid Data Valid Data Valid Data Valid tMRC CS2 |
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