FMP1617CA0(7)

CMOS LPRAM

Revision 0.1

Jun. 2006

7

Address

Data Out

tRC

Previous Data Valid

Data Valid

tAA

tOH

Address

tAA

tCO

tOH

tHZ

/CS1

tRC

1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced

to output voltage levels.

2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device

to device interconnection.

3. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 20us.

tBA

tOE

tOLZ

tBLZ

tLZ

Data Valid

High-Z

tBHZ

tOHZ

/UB, /LB

/OE

Data Out

CS2

1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced

to output voltage levels.

2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device

to device interconnection.

3. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 20us.

4. In case page address skew is over 3ns, tPAA will be out of spec.

A0~A3

tAA

tCO

tBA

tOE

High-Z

tHZ

tBHZ

tOHZ

/CS1

/UB, /LB

/OE

Data Out

tRC

A4~A20

tOH

tPC

tPC

tPC

tPC

tPC

tPC

tPC

tPAA

tPAA

tPAA

tPAA

tPAA

tPAA

tPAA

tLZ

tBLZ

tOLZ

Data Valid

Data Valid

Data Valid

Data Valid

Data Valid

Data Valid

Data Valid

Data Valid

tMRC

CS2