 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
CMS3216LAF Datasheet(PDF) 6 Page - FIDELIX |
|
||||||||||||||||||||||||||||||
CMS3216LAF Datasheet(HTML) 6 Page - FIDELIX |
|
|
6 / 46 page  Rev0.2, Jan. 2007 CMS3216LAx-75xx FUNCTIONAL DESCRIPTION The Fidelix 32Mb SDRAM is a dual-bank DRAM that operates at 2.3~3.3V and includes a synchronous inter- face (all signals are registered on the positive edge of the clock signal, CLK). Each of 16,777,216-bit banks is organized as 2,048 rows by 512 columns by 16 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a pro- grammed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be a c c e s s e d ( B S s e l e c t the ba nk, A0- A 10 select the row). The address bits (A0-A8) registered coincident with the READ or WRITE command are used to select the starting column location for the burst access.The SDRAM must be ini- tialized prior to normal operation. The following sections pro- vide detailed information regarding device initialization, register definition, command descriptions and device operation. Initialization SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Once power is applied to VDD and VDDQ(simultaneously) and the clock is stable (meets the clock specifications in the AC characteristics), the SDRAM requires a 100µs delay prior to issuing any command other than a COMMAND INHIBIT or NOP. The COMMAND INHIBIT or NOP should be applied at least once during the 100µs delay. After the 100µs delay, a PRECHARGE command should be applied. All banks must then be precharged, thereby placing the device in the all banks idle state. Once in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are complete, the SDRAM is ready for mode register programming. Because the mode register will power up in an unknown state, it should be loaded prior to applying any operational command. Refer to Figure 1. |
Similar Part No. - CMS3216LAF |
|
Similar Description - CMS3216LAF |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
