9

5279B–SEEPR–3/08

AT24C256B

5. Device Addressing

The 256K EEPROM requires an 8-bit device address word following a start condition to enable

the chip for a read or write operation (see Figure 5-1). The device address word consists of a

mandatory “1”, “0” sequence for the first four most significant bits as shown. This is common to

all two-wire EEPROM devices.

Figure 5-1.

Device Address

The next three bits are the A2, A1, A0 device address bits to allow as many as eight devices on

the same bus. These bits must compare to their corresponding hardwired input pins. The A2,

A1, and A0 pins use an internal proprietary circuit that biases them to a logic low condition if the

pins are allowed to float.

The eighth bit of the device address is the read/write operation select bit. A read operation is ini-

tiated if this bit is high, and a write operation is initiated if this bit is low.

Upon a compare of the device address, the EEPROM will output a “0”. If a compare is not made,

the device will return to a standby state.

DATA SECURITY: The AT24C256B has a hardware data protection scheme that allows the user

MSB

1

0

1

0

A2

A1

A0

R/W

LSB