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AT24HC02B-W-11 Datasheet(PDF) 7 Page - ATMEL Corporation |
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AT24HC02B-W-11 Datasheet(HTML) 7 Page - ATMEL Corporation |
7 / 19 page 7 5134E–SEEPR–3/08 AT24HC02B 2-WIRE SOFTWARE RESET: After an interruption in protocol, power loss or system reset, any two-wire part can be reset by following these steps: (a) Clock up to 9 cycles, (b) Look for SDA high in each cycle while SCL is high, (c) Create a start condition as SDA is high. The device is ready for next communication after above steps have been completed. Figure 5-3. Software Reset Figure 5-4. Bus Timing Figure 5-5. Write Cycle Timing Notes: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. Start bit Stop bit Start bit Dummy Clock Cycles SCL SDA 12 38 9 SCL SDA IN SDA OUT t F t HIGH t LOW t LOW t R t AA t DH t BUF t SU.STO t SU.DAT t HD.DAT t HD.STA t SU.STA t wr (1) STOP CONDITION START CONDITION WORDn ACK 8th BIT SCL SDA |
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