5

4983B–INDCO–10/08

ATA8403

Figure 4-1.

Tolerances of Frequency Modulation

Using C

tances on each side of the crystal of C

crystal of C

ation of ±21.5 kHz with worst case tolerances of ±16.8 kHz to ±28.0 kHz.

4.3

CLK Output

An output CLK signal is provided for a connected microcontroller. The delivered signal is CMOS

compatible if the load capacitance is lower than 10 pF.

4.3.1

Clock Pulse Take-over

The clock of the crystal oscillator can be used for clocking the microcontroller. A special feature

with ENABLE = H, and after 4 ms assumes the clock signal of the transmission IC, so that the

message can be sent with crystal accuracy.

4.3.2

Output Matching and Power Setting

The output power is set by the load impedance of the antenna. The maximum output power is

achieved with a load impedance of Z

resistive path to V

The delivered current pulse of the power amplifier is 7.7 mA. The maximum output power is

delivered to a resistive load of 475

Ω if the 0.53 pF output capacitance of the power amplifier is

compensated by the load impedance.

An optimum load impedance of:

Z

of 5.5 dBm.

The load impedance is defined as the impedance seen from the ATA8403’s ANT1, ANT2 into

the matching network. Do not confuse this large signal load impedance with a small signal input

impedance delivered as input characteristic of RF amplifiers and measured from the application

into the IC instead of from the IC into the application for a power amplifier.

Less output power is achieved by lowering the real parallel part of 475

Ω where the parallel imag-

inary part should be kept constant.

Output power measurement can be done with the circuit shown in Figure 4-2 on page 6. Note

that the component values must be changed to compensate for the individual board parasitics

until the ATA8403 has the right load impedance Z

damping of the cable used to measure the output power must be calibrated out.

XTAL