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ATA3745 Datasheet(PDF) 9 Page - ATMEL Corporation

Part # ATA3745
Description  UHF ASK/FSK Receiver
Download  30 Pages
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

ATA3745 Datasheet(HTML) 9 Page - ATMEL Corporation

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9
4901B–RKE–11/07
ATA3745
5.
Polling Circuit and Control Logic
The receiver is designed to consume less than 1 mA while being sensitive to signals from a
corresponding transmitter. This is achieved via the polling circuit. This circuit enables the sig-
nal path periodically for a short time. During this time, the bit check logic verifies the presence
of a valid transmitter signal. Only if a valid signal is detected does the receiver remain active
and transfer the data to the connected microcontroller. If there is no valid signal present, the
receiver is in sleep mode most of the time, resulting in low current consumption. This condition
is called polling mode. A connected microcontroller is disabled during that time.
All relevant parameters of the polling logic can be configured by the connected microcontrol-
ler. This flexibility enables the user to meet the specifications in terms of current consumption,
system response time, data rate, etc.
Regarding the number of connection wires to the microcontroller, the receiver is very flexible.
It can be either operated by a single bi-directional line to save ports to the connected micro-
controller, or it can be operated by up to three uni-directional ports.
5.1
Basic Clock Cycle of the Digital Circuitry
The complete timing of the digital circuitry and the analog filtering is derived from one clock.
Figure 5-1 shows how this clock cycle T
Clk is derived from the crystal oscillator (XTO) in com-
bination with a divider. The division factor is controlled by the logical state at pin MODE. As
described in “RF Front End” on page 4, the frequency of the crystal oscillator (f
XTO) is defined
by the RF input signal (f
RFin) which also defines the operating frequency of the local oscillator
(f
LO).
Figure 5-1.
Generation of the Basic Clock Cycle
Pin MODE can now be set in accordance with the desired clock cycle T
Clk. TClk controls the fol-
lowing application-relevant parameters:
• Timing of the polling circuit including bit check
• Timing of analog and digital signal processing
• Timing of register programming
• Frequency of the reset marker
• IF filter center frequency (f
IF0)
16
MODE
L: USA (:10)
H: Europe (:14)
XTO
Divider
:14/10
DVCC
XTO
fXTO
TCLK
15
14


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