7

4832D–RKE–12/07

ATA5278

The main element of this circuit is the parallel inverting stage which generates the clock signal in

conjunction with the external reference device. During power-down mode, these inverters are

shut down and the pull-down structure on the OSCI pin is active. As soon as the SPI enables the

oscillator, the pull-down is disabled and the inverters are powered up. Now, the clock signal

assessment stage monitors the signal on the OSCI pin. As soon as the amplitude and the period

reach acceptable values, one of the two inverters (i.e., the drivers) is shut down in order to

reduce power dissipation in the external reference device. Figure 3-5 illustrates the period

assessment.

Figure 3-5.

Oscillator Signal Assessment

3.5

I/O Voltage Interface

All digital I/O pins, including the reset input pin NRES, are passed through the internal voltage

interface before they reach their concerning blocks. This interface prevents possible compensa-

tion currents, as the control logic of the ATA5278 is supplied by the internal 5V regulator. It is

capable of handling I/O voltages between 3.15V and 5.5V, determined by the voltage applied to

the VIF pin.

The pins NRES and S_CS are additionally equipped with a pull-up and a pull-down structure

respectively in order to ensure a defined behavior of the ATA5278 in case of a broken connec-

tion. If the NRES line is broken, the pull-up structure keeps the input in passive state and normal

operation is possible. A broken S_CS line will cause a permanently disabled SPI and S_DO pin,

so communication between the microcontroller and other SPI bus members is still possible. For

further details on the voltage interface, please refer to the table “Electrical Characteristics” on

page 27.

t > t

LOW,max

t < t

LOW,max

Oscillator

enable signal

Clock signal for

internal logic

Clock signal for

internal logic

Second inverter

enable signal

OSCO signal