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10

XE1203F

4.1.6

Pattern recognition block

When in receiver mode, this feature is activated by setting RTParam_Pattern Configuration Register bit high. The

demodulated data signal is compared with a pattern stored in the PATParam_Pattern Configuration Register. The

PATTERN output pin is driven by the output of this comparator and is synchronized by DCLK. It is set to high when

a matching condition is detected, otherwise set to low. The PATTERN output is updated at the rising edge of DCLK.

The number of bits used for comparison is defined in the ADParam_Psize Configuration Register and the number of

tolerated errors for the pattern recognition is defined in the ADParam_Ptol register. Figure 4, below, illustrates the

pattern matching process.

Figure 4: Pattern Matching Operation.

4.1.7

RSSI

When enabled, this function provides a Received Signal Strength Indication based on the signal at the output of the

base-band filter. To enable the RSSI function, the RTParam_RSSI Configuration Register bit should be set to “1”.

When enabled, the status of the RSSI in the DataOut_RSSI register is a 2-bit word which can be read via the serial

signal at the output of the base-band filter stage, divided by the signal gain.

DataOut_RSSI

Description

0 0

≤ VTHR1

0 1

≤ VTHR2

1 0

≤ VTHR3

1 1

Table 5 RSSI status description

actual values), are selected with the RTParam_RSSIR Configuration Register bit. They provide an overall RSSI

range of typically 25 dB.

The timing diagram of an RSSI measurement is illustrated in the Figure 5 below. When the RSSI function has been

activated, the signal strength is periodically measured and the result is stored in the register DataOut_RSSI each

time this DataOut_RSSI register is read via the 3-wire serial interface. Note that TS_RS is the wake-up time

required after the function has been enabled to ensure that a valid reading of RSSI is obtained.