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CY7C331
2
I/O Resources (continued)
It should be noted that there are two ground connections (pins
8 and 21) which, together with VCC (pin 22) are located cen-
trally on the package. The reason for this placement and du-
al-ground structure is to minimize the ground-loop noise when
the outputs are driving simultaneously into a heavy capacitive
load.
The CY7C331 has twelve I/O macrocells (see
Figure 1). Each
macrocell has two D-type flip-flops. One is fed from the array,
and one from the I/O pin. For each flip-flop there are three
dedicated product terms driving the R, S, and clock inputs,
respectively. Each macrocell has one input to the array and for
each pair of macrocells there is one shared input to the array.
The macrocell input to the array may be configured to come
from the ‘Q’ output of either flip-flop.
Selection Guide
Generic Part
Number
ICC1 (mA)
tPD (ns)
tS (ns)
tCO (ns)
Com’l
Mil
Com’l
Mil
Com’l
Mil
Com’l
Mil
CY7C331–20
130
20
12
20
CY7C331–25
120
160
25
25
12
15
25
25
CY7C331–30
150
30
15
30
CY7C331–40
150
40
20
40
Pin Configuration
25
24
23
22
21
20
19
5
6
7
8
9
10
11
121314 1516 1718
4 3 2
2827 26
1
C331–2
I4
I5
I6
I7
I8
I9
GND
I/O3
I/O4
I/O5
VCC
GND
I/O6
I/O7
TopView
Figure 1. I/O Macrocell
TO PIN 14 (INVERTED)
OE PTERM
OUT SET PTERM
0
1 S
O
C0
TO I/O PIN
0
1 S
O
S
R
D Q
QB
OUTPUT FLIP–FLOP
OUT CLK PTERM
IN CLK PTERM
IN SET PTERM
OUT RESET PTERM
S
R
D
Q
QB
0
1
S
O
C1
0
1
S
O
TO INPUT BUFFER
IN RESET PTERM
XOR PTERM
OR PTERMS
INPUT MUX
TO SHARED
INPUT FLIP–FLOP
TO PIN 14 (INVERTED)
C331–3
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