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CY7C335-66WC Datasheet(PDF) 3 Page - Cypress Semiconductor

Part # CY7C335-66WC
Description  Universal Synchronous EPLD
Download  17 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C335-66WC Datasheet(HTML) 3 Page - Cypress Semiconductor

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CY7C335
3
C6
Dedicated Input
Register Clock
Select MUX
12 Bits, 1 Per
Dedicated Input
Cell
0—Virgin State
ICLK1 Controls the Input Register I/O Macrocell
Dedicated Input Register Clock Input
1—Programmed
ICLK2 Controls the Input Register I/O Macrocell
Dedicated Input Register Clock Input
C7
Input Register
Bypass MUX—
Input Cell
12 Bits, 1 Per
Dedicated Input
Cell
0—Virgin State
Selects Input to Array from Input Register
1—Programmed
Selects Input to Array from Input Pin
C8
ICLK2 Select
MUX
1 Bit
0—Virgin State
Input Clock 2 Controlled by Pin 2
1—Programmed
Input Clock 2 Controlled by Pin 3
C9
ICLK1 Select
MUX
1 Bit
0—Virgin State
Input Clock 1 Controlled by Pin 2
1—Programmed
Input Clock 1 Controlled by Pin 1
C10
SCLK2 Select
MUX
1 Bit
0—Virgin State
State Clock 2 Grounded
1—Programmed
State Clock 2 Controlled by Pin 3
CX
(11–16)
I/O Macrocell
Pair Input
Select MUX
6 Bits, 1 Per
I/O Macrocell
Pair
0—Virgin State
Selects Data from I/O Macrocell Input Path of
Macrocell A of Macrocell Pair
1—Programmed
Selects Data from I/O Macrocell Input Path of
Macrocell B of Macrocell Pair
Table 1. Architecture Configuration Bits (continued)
Architecture
Configuration Bit
Number of Bits
Value
Function
Figure 1. CY7C335 Input Macrocell
C335–4
ICLK1
ICLK2
Q
D
C6
1
0
INPUTREGISTER
INPUT
CLOCK
MUX
TO ARRAY
INPUT
PIN
C7
1
0
INPUT
REG
BYPASS
MUX


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