CY7C335
8
Commercial AC Characteristics
7C335–100
7C335–83
7C335–66
7C335–50
Parameter
Description
Min.
Max.
Min.
Max.
Min. Max.
Min.
Max.
Unit
Combinatorial Mode Parameters
tPD
Input to Output Propagation Delay
15
15
20
25
ns
tEA
Input to Output Enable
15
15
20
25
ns
tER
Input to Output Disable
15
15
20
25
ns
Input Registered Mode Parameters
tWH
Input and Output Clock Width HIGH[5]
4
5
6
8
ns
tWL
Input and Output Clock Width LOW[5]
4
5
6
8
ns
tIS
Input or Feedback Set-Up Time to Input Clock
2
2
2
3
ns
tIH
Input Register Hold Time from Input Clock
2
2
2
3
ns
tICO
Input Register Clock to Output Delay
18
18
20
25
ns
tIOH
Output Data Stable Time from Input Clock
3
3
3
3
ns
tIOH – tIH
33x
Output Data Stable from Input Clock Minus Input
Register Hold Time for 7C335[6]
0
0
0
0
ns
tPZX
Pin 14 Enable to Output Enabled
12
12
15
20
ns
tPXZ
Pin 14 Disable to Output Disabled
12
12
15
20
ns
fMAX1
Maximum Frequency of (2) CY7C335s in Input Reg-
istered Mode (Lowest of 1/(tICO+tIS) &
1/(tWL+tWH))
[5]
50
50
45.4
35.7
MHz
fMAX2
Maximum Frequency Data Path in Input Registered
Mode (Lowest of (1/(tICO), 1/(tWH+tWL),
1/(tIS+tIH))
[5]
55.5
55.5
50
40
MHz
tICEA
Input Clock to Output Enabled
17
17
20
25
ns
tICER
Input Clock to Output Disabled
15
15
20
25
ns
Output Registered Mode Parameters
tCEA
Output Clock to Output Enabled[5]
17
17
20
25
ns
tCER
Output Clock to Output Disabled[5]
15
15
20
25
ns
tS
Output Register Input Set-Up Time from Output
Clock
8
9
12
15
ns
tH
Output Register Input Hold Time from Output Clock
0
0
0
0
ns
tCO
Output Register Clock to Output Delay
9
10
12
15
ns
tCO2
Input Output Register Clock or Latch Enable to
Combinatorial Output Delay (Through Logic Array)[5]
17
18
23
30
ns
tOH
Output Data Stable Time from Output Clock
2
2
2
2
ns
tOH2
Output Data Stable Time From Output Clock
(Through Memory Array)[5]
3
3
3
3
ns
tOH2–tIH
Output Data Clock Stable Time From Output Clock
Minus Input Register Hold Time[5]
0
0
0
0
ns
fMAX3
Maximum Frequency with Internal Feedback in Out-
put Registered Mode[5]
100
83.3
66.6
50
MHz
fMAX4
Maximum Frequency of (2) CY7C335s in Output
Registered Mode (Lowest of 1/(tCO + tS) & 1/(tWL +
tWH))
[5]
58.8
50
41.6
33.3
MHz
fMAX5
Maximum Frequency Data Path in Output Regis-
tered Mode (Lowest of 1/(tCO), 1/(tWL + tWH), 1/(tS +
tH))
[5]
111
100
83.3
62.5
MHz
tOH – tIH
33x
Output Data Stable from Output Clock Minus Input
Register Hold Time for 7C335[6]
0
0
0
0
ns
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