5

 2005 Semtech Corp.

www.semtech.com

PROTECTION PRODUCTS

SR05

PIN Descriptions

For negative events, the bottom diode will be biased

when the voltage exceeds the V

At first

approximation, the clamping voltage due to the charac-

teristics of the protection diodes is given by:

V

(for positive duration pulses)

V

(for negative duration pulses)

However, for fast rise time transient events, the

effects of parasitic inductance must also be consid-

ered as shown in Figure 2. Therefore, the actual

clamping voltage seen by the protected circuit will be:

V

V

(for negative duration pulses)

ESD current reaches a peak amplitude of 30A in 1ns

for a level 4 ESD contact discharge per IEC 61000-4-2.

Therefore, the voltage overshoot due to 1nH of series

inductance is:

V = L

-9

Example:

Consider a V

steering diode and a series trace inductance of 10nH.

The clamping voltage seen by the protected IC for a

positive 8kV (30A) ESD pulse will be:

V

This does not take into account that the ESD current is

directed into the supply rail, potentially damaging any

components that are attached to that rail. Also note

that it is not uncommon for the V

exceed the damage threshold of the protected IC. This

is due to the relatively small junction area of typical

discrete components. It is also possible that the

power dissipation capability of the discrete diode will

be exceeded, thus destroying the device.

The RailClamp is designed to overcome the inherent

disadvantages of using discrete signal diodes for ESD

suppression. The RailClamp’s integrated TVS diode

helps to mitigate the effects of parasitic inductance in

Figure 1 - “Rail-

Figure 1 - “Rail-

Figure 1 - “Rail-

Figure 1 - “Rail-

Figure 1 - “Rail-TTTTTo-Rail” Pr

o-Rail” Pr

o-Rail” Pr

o-Rail” Pr

o-Rail” Proooootttttection T

ection T

ection T

ection T

ection Topology

opology

opology

opology

opology

(First Approximation)

(First Approximation)

(First Approximation)

(First Approximation)

(First Approximation)

Figure 2 - The Effects of Parasitic Inductance

Figure 2 - The Effects of Parasitic Inductance

Figure 2 - The Effects of Parasitic Inductance

Figure 2 - The Effects of Parasitic Inductance

Figure 2 - The Effects of Parasitic Inductance

When Using Discrete Components to Implement

When Using Discrete Components to Implement

When Using Discrete Components to Implement

When Using Discrete Components to Implement

When Using Discrete Components to Implement

Rail-

Rail-

Rail-

Rail-

Rail-TTTTTo-Rail Pr

o-Rail Pr

o-Rail Pr

o-Rail Pr

o-Rail Proooootttttection

ection

ection

ection

ection

Figure 3 - Rail-

Figure 3 - Rail-

Figure 3 - Rail-

Figure 3 - Rail-

Figure 3 - Rail-TTTTTo-Rail Pr

o-Rail Pr

o-Rail Pr

o-Rail Pr

o-Rail Proooootttttection Using

ection Using

ection Using

ection Using

ection Using

RailClam

RailClam

RailClam

RailClam

RailClamp T

p T

p T

p T

p T VVVVVS Arra

S Arra

S Arra

S Arra

S Arrays

ys

ys

ys

ys

Applications Information (continued)