DP83849ID datasheet(9/98 Pages) NSC

Part #	DP83849ID

Description	PHYTER짰 DUAL Industrial Temperature with Fiber Support (FX) Dual Port 10/100 Mb/s Ethernet Physical Layer Transceiver

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Manufacturer	NSC [National Semiconductor (TI)]

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1.0 Pin Descriptions

The DP83849ID pins are classified into the following inter-

face categories (each interface is described in the sections

that follow):

— Serial Management Interface

— MAC Data Interface

— Clock Interface

— LED Interface

—JTAG Interface

— Reset and Power Down

— Strap Options

— 10/100 Mb/s PMD Interface

— Special Connect Pins

— Power and Ground pins

Note: Strapping pin option. Please see Section 1.7 for strap

definitions.

All DP83849ID signal pins are I/O cells regardless of the

particular use. The definitions below define the functionality

of the I/O cells for each pin.

1.1 Serial Management Interface

1.2 MAC Data Interface

Type: I

Input

Type: O

Output

Type: I/O

Input/Output

Type OD

Open Drain

Type: PD,PU Internal Pulldown/Pullup

Type: S

Strapping Pin (All strap pins have weak in-

ternal pull-ups or pull-downs. If the default

strap value is to be changed then an exter-

nal 2.2 k

Ω resistor should be used. Please

see Section 1.7 for details.)

Signal Name

Type

Pin #

Description

MDC

I

67

MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO

management data input/output serial interface which may be asyn-

chronous to transmit and receive clocks. The maximum clock rate is

25 MHz with no minimum clock rate.

MDIO

I/O

66

MANAGEMENT DATA I/O: Bi-directional management instruc-

tion/data signal that may be sourced by the station management entity

or the PHY. This pin requires a 1.5 k

Ω pullup resistor.

Signal Name

Type

Pin #

Description

TX_CLK_A

TX_CLK_B

O

12

50

MII TRANSMIT CLOCK: 25 MHz Transmit clock output in 100 Mb/s

mode or 2.5 MHz in 10 Mb/s mode derived from the 25 MHz reference

clock.

Unused in RMII mode. The device uses the X1 reference clock input

as the 50 MHz reference for both transmit and receive.

SNI TRANSMIT CLOCK: 10 MHz Transmit clock output in 10 Mb SNI

mode. The MAC should source TX_EN and TXD_0 using this clock.

TX_EN_A

TX_EN_B

I

13

49

MII TRANSMIT ENABLE: Active high input indicates the presence of

valid data inputs on TXD[3:0].

RMII TRANSMIT ENABLE: Active high input indicates the presence

of valid data on TXD[1:0].

SNI TRANSMIT ENABLE: Active high input indicates the presence of

valid data on TXD_0.

TXD[3:0]_A

TXD[3:0]_B

I

17,16,15,14

45,46,47,48

MII TRANSMIT DATA: Transmit data MII input pins, TXD[3:0], that

accept data synchronous to the TX_CLK (2.5 MHz in 10 Mb/s mode

or 25 MHz in 100 Mb/s mode).

RMII TRANSMIT DATA: Transmit data RMII input pins, TXD[1:0],

that accept data synchronous to the 50 MHz reference clock.

SNI TRANSMIT DATA: Transmit data SNI input pin, TXD_0, that ac-

cept data synchronous to the TX_CLK (10 MHz in 10 Mb/s SNI mode).

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DP83849ID Datasheet(PDF) 9 Page - National Semiconductor (TI)

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