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U2794B-NFSH Datasheet(PDF) 4 Page - ATMEL Corporation |
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U2794B-NFSH Datasheet(HTML) 4 Page - ATMEL Corporation |
4 / 15 page 4 4653F–CELL–11/08 U2794B 6. Electrical Characteristics Test conditions (unless otherwise specified); V S = 5V, Tamb = 25°C, referred to test circuit System impedance ZO = 50Ω, fiLO = 950 MHz, PiLO = –10 dBm No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* 1.1 Supply-voltage range 5, 6 VS 4.75 5.25 V A 1.2 Supply current 5, 6 IS 22 30 35 mA A 2 Power-down Mode 2.1 “OFF” mode supply current VPU ≤ 0.5V V PU = 1.0 V (1) 14, 5 6 I SPU ≤ 1 20 µA µA B D 3 Switch Voltage 3.1 “Power ON” 14 V PON 4V D 3.2 “Power DOWN” 14 V POFF 1V D 4 LO Input, LO in 4.1 Frequency range 17 f iLO 70 1000 MHz D 4.2 Input level (2) 17 P iLO –12 –10 –5 dBm D 4.3 Input impedance See Figure 6-10 17 Z iLO 50 Ω D 4.4 Voltage standing wave ratio See Figure 6-3 17 VSWRLO 1.2 2 D 4.5 Duty-cycle range 17 DCR LO 0.4 0.6 D 5RF Input, RF in 5.1 Noise figure (DSB) symmetrical output at 950 MHz(3) at 100 MHz 7, 8 NF 12 10 dB D 5.2 Frequency range fiRF = fiLO ±BWYQ 7, 8 fiRF 40 1030 MHz D 5.3 –1 dB input compression point High gain Low gain 7, 8 P1dBHG P 1dBLG –8 +3.5 dBm D 5.4 Second order IIP (4) 7, 8 IIP 2HG 35 dBm D 5.5 Third order IIP High gain Low gain 7, 8 IIP 3HG IIP3LG +3 +13 dBm D 5.6 LO leakage Symmetric input Asymmetric input 7, 8 L OL ≤ –60 ≤ –55 dBm D 5.7 Input impedance see Figure 6-10 7, 8 ZiRF 500II0.8 ΩIIpF D *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. During power-down status a load circuitry with DC-isolation to GND is assumed, otherwise a current of I ≈ (VS –0.8V)/RI has to be added to the above power-down current for each output I, IX, Q, QX. 2. The required LO-Level is a function of the LO frequency (see Figure 6-6). 3. Measured with input matching. For 950 MHz, the optional transmission line T3 at the RF input may be used for this pur- pose. Noise figure measurements without using the differential output signal result in a worse noise figure. 4. Using pins 7 and 8 as a symmetric RF input, the second-order IIP can be improved. 5. Due to test board parasitics, this bandwidth may be reduced and not be equal for I, IX, Q, QX. If symmetry and full band- width is required, the lowpass pins 3, 4 and 9, 10 should be isolated from the board. the bandwidth of the I/Q outputs can be increased further by using a resistor between pins 3, 4, 9 and 10. These resistors shunt the internal loads of RI ~ 5.4 k Ω. The decrease in gain here has to be considered. 6. The internal current of the output emitter followers is 0.6 mA. This reduces the undistorted output voltage swing at a 50 Ω load to approximately 30 mV. For low signal distortion the load impedance should be RI ≥ 5 kΩ. 7. Referred to the level of the output vector 8. The low-gain status is achieved with an open or high-ohmic pin 11. A recommended application circuit for switching between high and low gain status is shown in Figure 6-1. I 2 Q 2 + |
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