10

4670D–BCD–04/07

T6817

5.13

Open load detection

current

Input register bit 13

(OLD) = low, output off

12, 14,

16

I

HS1–3

–150

–30

µA

A

5.14

Open load detection

current ratio

I

LS1–3/

I

HS1–3

1.2

A

5.15

Open load detection

threshold

Input register bit 13

(OLD) = low, output off

8, 15,

17

V

LS1–3

0.6

2

V

A

5.16

Open load detection

threshold

Input register bit 13

(OLD) = low, output off

12, 14,

16

V

HS1–3

0.6

2

V

A

5.17

Output switch on

0.5

ms

A

5.18

Output switch off

R

t

doff

1ms

A

6

Inhibit Input

6.1

Input voltage low

level threshold

5V

IL

0.3

×

V

VCC

VA

6.2

Input voltage high

level threshold

0.7

×

V

VCC

VA

6.3

Hysteresis of input

voltage

5

∆V

I

100

700

mV

A

6.4

Pull-down current

10

80

µA

A

7

Serial Interface – Logic Inputs DI, CLK, CS

7.1

Input voltage

low-level threshold

2-4

0.3

×

V

VCC

VA

7.2

Input voltage

high-level threshold

2-4

0.7

×

VA

7.3

Hysteresis of input

voltage

2-4

∆V

I

50

500

mV

A

7.4

Pull-down current pin

DI, CLK

2, 4

250

µA

A

7.5

Pull-up current

pin CS

3

–50

–2

µA

A

8

Serial Interface - Logic Output DO

8.1

Output voltage low

level

I

18

V

DOL

0.5

V

A

8.2

Output voltage high

level

18

–1V

VA

8.3

Leakage current

(tri-state)

V

18

–10

10

µA

A

8.

Electrical Characteristics (Continued)

No.

Parameters

Test Conditions

Pin

Symbol

Min.

Typ.

Max.

Unit

Type*

*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note:

1. Delay time between rising edge of CS after data transmission and switch on/off output stages to 90% of final level