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4261F–AERO–08/08

ATC18RHA

Design Phases

The development of an ASIC chip can be split into 4 main phases.

A meeting is set between each phase.

Figure 2. Design Management Phases

•

Phase 1: Feasibility study

Meeting: Design Start Review (DSR)

•

Phase 2: Logic design

Meeting: Logic Review (LR)

•

Phase 3: Physical design

Meeting: Design Review (DR)

•

Phase 4: Prototypes manufacturing and test

During the review meetings, the conformity of the design to Atmel rules is checked and acknowl-

edged in formal documents, and the data is transferred to the next phase. The content of each

phase is described in the following sections. The responsibility of each step is dependent on the

design flow. The flows will be described later on.

Phase 1

Feasibility Study

At this step, the customer is asked to provide:

• the project identification (name, type)

• an overall description of the functions of the ASIC

• an estimation of the number of logic gates

• an estimation of the number, size and type of the memory blocks

• other hard/compiled blocks

• macro-cells (PLL)

• the number of I/Os without supply (number of LVDS buffers if requested)

• the number of expected supply buffers for periphery (according drive, simultaneous switching,

load...)

• number of simultaneous switching scan FF to determine supply buffers for the core

• preliminary net-list (*)