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ACS8525AP Datasheet(PDF) 1 Page - Semtech Corporation |
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ACS8525AP Datasheet(HTML) 1 Page - Semtech Corporation |
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1 / 112 page  Revision 1.00/September 2007 © Semtech Corp. Page 1 www.semtech.com ACS8525A LC/P ADVANCED COMMUNICATIONS FINAL Line Card Protection Switch for SONET/SDH Systems ADVANCED COMMS & SENSING FINAL DATASHEET The ACS8525A is a highly integrated, single-chip solution for “Hit-less” protection switching of SEC (SDH/SONET Equipment Clock) + Sync clock “Groups”, from Master and Slave SETS clock cards and a third (Stand-by) source, for Line Cards in a SONET or SDH Network Element. The ACS8525A has fast activity monitors on the SEC clock inputs and will implement automatic system protection switching against the Master clock failure. The selection of the Master/Slave input can be forced by a Force Fast Switch pin. If both the Master and Slave input clocks fail, the Stand-by “Group” is selected or, if no Stand-by is available, the device enters Digital Holdover mode. The ACS8525A can perform frequency translation, converting, for example, an 8 kHz SEC input clock from a backplane into a 155.52 MHz clock for local line cards. Master and Slave SEC inputs to the device support TTL/CMOS and PECL/LVDS. The Stand-by SEC and three Sync inputs are TTL/CMOS only. The ACS8525A generates two SEC clock outputs, via one PECL/LVDS and one TTL/CMOS port, with spot frequencies from 2 kHz up to 311.04 MHz (up to 155.52 MHz on the TTL/CMOS port). It also provides an 8 kHz Frame Sync and a 2 kHz Multi-Frame Sync signal output with programmable pulse width and polarity. The ACS8525 includes a Serial Port, which can be SPI compatible, providing access to the configuration and status registers for device setup. IEEE 1149.1 JTAG Boundary Scan is supported. SONET/SDH applications up to OC-3/STM-1 bit rate. Switches between grouped inputs (SEC/Sync pairs). Inputs: three SECs at any of 2, 4, 8 kHz (and N x 8 kHz multiples up to 155.52 MHz), plus Frame Sync/Multi- Frame Sync. Outputs: two SEC clocks at any of several spot frequencies from 2 kHz up to 77.76 MHz via the TTL/CMOS port and up to 311.04 MHz via the PECL/LVDS port. Selectable clock I/O port technologies. Modes for E3/DS3 and multiple E1/DS1 rate output clocks. Frequency translation of SEC input clock to a different local line card clock. Robust input clock source activity monitoring on all inputs. Supports Free-run, Locked and Digital Holdover modes of operation. Automatic “Hit-less” source switchover on loss of input. External force fast switch between SEC1/SEC2 inputs. Phase Build-out for output clock phase continuity during input switchover. PLL “Locked” and “Acquisition” bandwidths individually selectable from 18, 35 or 70 Hz. Serial interface for device set-up. Single 3.3 V operation. Operating temperature (ambient) of 0 to +70°C. Available in LQFP 64 package. Lead (Pb)-free version available (ACS8525T), RoHS and WEEE compliant. Figure 1 Block Diagram of the ACS8525A LC/P Block Diagram Description Features IEEE 1149.1 JTAG Chip Clock Generator TCK TDI TMS TRST TDO F8525D_001BLOCKDIA_05 Selector DPLL1 DPLL2 E1/DS1 Synthesis APLL2 APLL3 APLL 1 01 and 02: E1/DS1 (2.048/1.544 MHz) and frequency multiples: 1.5x, 2x, 3x, 4x, 6x, 12x, 16x, and 24x E1/DS1 E3/DS3, 2 kHz, 8 kHz. and OC-N* rates: OC-1 51.84 MHz OC-3 155.52 MHz and derivatives: 6.48 MHz (O2 port only) 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz (01 port only) 311.04 MHz (01 port only) 3 x SEC/Sync Input Groups SEC1 & SEC2: TTL/PECL/LVDS, SEC3 and all Syncs TTL only SEC Inputs: Programmable Frequencies 2 kHz, 4 kHz, N x 8 kHz 1.544/2.048 MHz 6.48 MHz 19.44 MHz 25.92 MHz 38.88 MHz 51.84 MHz 77.76 MHz 155.52 MHz FrSync 8 kHz (TTL) Output Port Frequency Selection Priority Table Register Set Digital Feedback Serial Interface Port TCXO or XO Input SEC Port Monitors and Input Selection Control Master Slave Stand-by 01 (PECL/LVDS) 02 (TTL) MFrSync 2 kHz (TTL) SEC Outputs: Sync Outputs: SEC1 SYNC1 SEC2 SYNC2 SEC3 SYNC3 MUX 2 MUX 1 |
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