ACS8515P datasheet(8/50 Pages) SEMTECH

Part #	ACS8515P

Description	Line Card Protection Switch for SONET or SDH Network Elements

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Manufacturer	SEMTECH [Semtech Corporation]

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Revision 2.01/December 2005

Semtech Corp.

www.semtech.com

8

ACS8515 Rev2.1 LC/P

ADVANCED COMMUNICATIONS

FINAL

+/- 50 ppm adjustment would be sufficient to

cope with most crystals, in fact the range is an

order of magnitude larger due to the use of

two 8 bit register locations. The setting of the

conf_nominal_frequency register allows for this

adjustment. An increase in the register value

increases the output frequencies by 0.02 ppm

for each LSB step. The default value (in decimal)

is 39321. The minimum being 0 and the

maximum 65535, giving a -700 ppm to +500

ppm adjustment range of the output

frequencies.

For example, if the crystal was oscillating at

12.8 MHz + 5 ppm, then the calibration value

in the register to give a - 5 ppm adjustment in

output frequencies to compensate for the

crystal inaccuracy, would be :

39321 - (5 / 0.02) = 39071 (decimal)

The ACS8515 supports up to three individual input

reference clock sources via TTL/CMOS and PECL/

LVDS technologies. These interface technologies

support +3.3 V and +5 V operation.

Input Reference Clock Ports

The input reference clock ports are arranged in

groups. Group one comprises a TTL port (SEC1)

and a PECL/LVDS port (SEC1POS and

SEC1NEG). Group two comprises a TTL port

(SEC2) and a PECL/LVDS port (SEC2POS and

SEC2NEG). Group three comprises a TTL port

(SEC3). For group one and group two, only one

of the two input ports types must be active at

any time, the other must not be driven by a

reference input. Unused PECL/LVDS differential

inputs should be fixed with one input high (VDD)

and the other low (GND), or set in LVDS mode

and left floating (in which case one input is

internally pulled high and the other low).

SDH and SONET networks use different default

frequencies; the network type is selectable

using the config_mode register 34 Hex, bit 2.

For SONET, config_mode register 34 Hex, bit 2

= 1, for SDH config_mode register 34 Hex, bit

2 = 0. On power-up or by reset, the default will

be set by the state of the SONSDHB pin (pin

64). Specific frequencies and priorities are set

by configuration.

The TTL ports (compatible also with CMOS

signals) support clock speeds up to 100 MHz,

with the highest spot frequency being 77.76

MHz. Clock speeds above 100 MHz should not

be applied to the TTL ports. The PECL/LVDS

ports support the full range of clock speeds,

up to 155.52 MHz.

The actual spot frequencies supported are:

•2 kHz

•4 kHz

•8 kHz (and N x 8 kHz),

•1.544 MHz (SONET)/2.048 MHz (SDH),

•6.48 MHz,

•19.44 MHz,

•25.92 MHz,

•38.88 MHz,

•51.84 MHz,

•77.76 MHz,

•155.52 MHz.

The frequency selection is programmed via the

cnfg_ref_source_frequency register.

The

internal DPLL will normally lock to the selected

input at the frequency of the input, eg.

19.44 MHz will lock the DPLL phase

comparisons at 19.44 MHz. It is, however,

possible to utilise an internal pre-divider to the

DPLL to divide the input frequency before it is

used for phase comparisons in the DPLL. This

pre-divider can be used in one of 2 ways;

1. Any of the supported spot frequencies can be divided to

8 kHz by setting the ‘lock8K’ bit (bit 6) in the appropriate

cnfg_ref_source_frequency register location. For good jitter

tolerance for all frequencies and for operation at

19.44 MHz and above, use lock8K. It is possible to choose

which edge of the 8kHz input to lock to, by setting the

appropriate bit of the cnfg_control1 register.

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