ACS8520T datasheet(10/150 Pages) SEMTECH

Part #	ACS8520T

Description	Synchronous Equipment Timing Source for Stratum 3/4E/4 and SMC Systems

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ADVANCED COMMUNICATIONS

FINAL

DATASHEET

Revision 3.02/October 2005 © Semtech Corp.

Page 10

www.semtech.com

ACS8520 SETS

method allows for example, a master and a slave device

to be in precise alignment.

The ACS8520 also supports Sync pulse references of

4 kHz or 8 kHz although in these cases frequencies lower

than the Sync pulse reference may not necessarily be in

phase.

Input Reference Clock Ports

Table 4 gives details of the input reference ports, showing

the input technologies and the range of frequencies

supported on each port; the default spot frequencies and

default priorities assigned to each port on power-up or by

reset are also shown. Note that SDH and SONET networks

use different default frequencies; the network type is pin-

selectable (using either the SONSDHB pin or via

software). Specific frequencies and priorities are set by

configuration.

SDH and SONET networks use different default

frequencies; the network type is selectable using the

cnfg_input_mode Reg. 34 Bit 2, ip_sonsdhb.

For SONET, ip_sonsdhb = 1

For SDH, ip_sonsdhb = 0

On power-up or by reset, the default will be set by the state

of the SONSDHB pin (pin 100). Specific frequencies and

priorities are set by configuration.

The frequency selection is programmed via the

cnfg_ref_source_frequency register (Reg. 20 - Reg. 2D).

Locking Frequency Modes

There are three locking frequency modes that can be

configured: Direct Lock, Lock 8k and DivN.

Direct Lock Mode

In Direct Lock Mode, the internal DPLL can lock to the

selected input at the spot frequency of the input, for

example 19.44 MHz performs the DPLL phase

comparisons at 19.44 MHz.

In Lock8K and DivN modes (and for special case of

155 MHz), an internal divider is used prior to the DPLL to

divide the input frequency before it is used for phase

comparisons in the DPLL.

Lock8K Mode

Lock8K mode automatically sets the divider parameters

to divide the input frequency down to 8 kHz. Lock8K can

only be used on the supported spot frequencies (see

Table 4 Note(i)). Lock8k mode is enabled by setting the

Lock8k bit (Bit 6) in the appropriate

cnfg_ref_source_frequency register location. Using lower

frequencies for phase comparisons in the DPLL results in

a greater tolerance to input jitter.It is possible to choose

which edge of the input reference clock to lock to, by

setting 8K edge polarity (Bit 2 of Reg. 03, test_register1).

DivN Mode

In DivN mode, the divider parameters are set manually by

configuration (Bit 7 of the cnfg_ref_source_frequency

register), but must be set so that the frequency after

division is 8 kHz.

The DivN function is defined as:

DivN = “Divide by N+ 1”, i.e. it is the dividing factor used

for the division of the input frequency, and has a value of

(N+1) where N is an integer from 1 to 12499 inclusive.

Therefore, in DivN mode the input frequency can be

divided by any integer value between 2 to 12500.

Consequently, any input frequency which is a multiple of

8 kHz, between 8 kHz to 100 MHz, can be supported by

using DivN mode.

Note...Any reference input can be set to use DivN

independently of the frequencies and configurations of the

other inputs. However only one value of N is allowed, so all

inputs with DivN selected must be running at the same

frequency.

DivN Examples

(a) To lock to 2.000 MHz:

(i)

Set the cnfg_ref_source_frequency register to

10XX0000 (binary) to enable DivN, and set the

frequency to 8 kHz - the frequency required after

division. (XX = “Leaky Bucket” ID for this input).

(ii) To achieve 8 kHz, the 2 MHz input must be

divided by 250. So, if DivN = 250 = (N + 1)

then N must be set to 249. This is done by writing

F9 hex (249 decimal) to the DivN register pair

Reg. 46/47.

(b) To lock to 10.000 MHz:

(i)

The cnfg_ref_source_frequency register is set to

10XX0000 (binary) to set the DivN and the

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