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ACS8510REV2.1 Datasheet(PDF) 1 Page - Semtech Corporation |
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ACS8510REV2.1 Datasheet(HTML) 1 Page - Semtech Corporation |
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1 / 76 page  S SS SSynchronous EEEEEquipment TTTTTiming S SS SSource for SONET or SDH Network Elements ACS8510 Rev2.1 SETS Description Description Description Description Description Features Features Features Features Features Block Diagram Block Diagram Block Diagram Block Diagram Block Diagram The ACS8510 is a highly integrated, single-chip solution for the Synchronous Equipment Timing Source (SETS) function in a SONET or SDH Net- work Element. The device generates SONET or SDH Equipment Clocks (SEC) and frame synchro- nization clocks. The ACS8510 is fully compliant with the required specifications and standards. The device supports Free-run, Locked and Holdover modes. It also supports all three types of reference clock source: recovered line clock, PDH network, and node synchronization. The ACS8510 generates independent SEC and BITS clocks, an 8 kHz Frame Synchronization clock and a 2 kHz Multi-Frame Synchronization clock. Two ACS8510 devices can be used together in a Master/Slave configuration mode allowing sys- tem protection against a single ACS8510 failure. A microprocessor port is incorporated, providing access to the configuration and status registers for device setup and monitoring. The ACS8510 supports IEEE 1149.1 JTAG boundary scan. Rev2.1 adds choice of edge alignment for 8kHz input, as well as a low jitter n x E1/DS1 output mode. Other minor changes are made, with all described in Appendix A. ADVANCED COMMUNICATIONS FINAL Revision 2.00/September 2003 Semtech Corp. www.semtech.com •Suitable for Stratum 3E*, 3, 4E and 4 SONET or SDH Equipment Clock (SEC) applications •Meets AT&T, ITU-T, ETSI and Telcordia specifications •Accepts 14 individual input reference clocks •Generates 11 output clocks •Supports Free-run, Locked and Holdover modes of operation •Robust input clock source quality monitoring on all inputs •Automatic ‘hit-less’ source switchover on loss of input •Phase build out for output clock phase continuity during input switchover and mode transitions •Microprocessor interface - Intel, Motorola, Serial, Multiplexed, EPROM •Programmable wander and jitter tracking attenuation 0.1 Hz to 20 Hz •Support for Master/Slave device configuration alignment and hot/standby redundancy •IEEE 1149.1 JTAG Boundary Scan •Single +3.3 V operation, +5 V I/O compatible •Operating temperature (ambient) -40°C to +85°C •Available in 100 pin LQFP package * Meets Holdover requirements, lowest bandwidth 0.1 Hz. Figure 1. Simple Block Diagram Figure 1. Simple Block Diagram Figure 1. Simple Block Diagram Figure 1. Simple Block Diagram Figure 1. Simple Block Diagram DPLL/Freq. Synthesis TOUT0 selector TOUT4 selector Chip Clock Generator Divider PFD DPLL/Freq. Synthesis Divider Monitors Digital Loop Filter APLL Frequency Dividers Microprocessor Port 2 x AMI 10 x TTL 2 x PECL/LVDS Programmable; 64/8kHz 2kHz 4kHz N x 8kHz 1.544/2.048MHz 6.48MHz 19.44MHz 25.92MHz 38.88MHz 51.84MHz 77.76MHz 155.52MHz DTO Digital Loop Filter PFD 1 x AMI 6 x TTL 2 x PECL/LVDS Programmable: 64/8kHz 1.544/2.048MHz 3.088/4.096MHz 6.176/8.182MHz 12.352/16.384MHz 6.48MHz 19.44MHz 25.92MHz 38.88MHz 51.84MHz 77.76MHz 155.52MHz 311.04MHz 2kHz MFrSync 8kHz FrSync Input Ports 14xSEC MFrSync Output Ports TCXO (*OCXO) IEEE 1149.1 JTAG TCK TDI TMS TRST TDO Priority Table Register Set DTO 9xSEC FrSync MFrSync |
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