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ATAR890X-YYY-TKSYZ Datasheet(PDF) 3 Page - ATMEL Corporation |
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ATAR890X-YYY-TKSYZ Datasheet(HTML) 3 Page - ATMEL Corporation |
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3 / 75 page  3 ATAR090/ATAR890 4696D–4BMCU–12/04 Introduction The ATAR090/ATAR890 are members of Atmel’s family of 4-bit single-chip microcon- trollers. They contain ROM, RAM, parallel I/O ports, one 8-bit programmable multi- function timer/counters, voltage supervisor, interval timer with watchdog function and a sophisticated on-chip clock generation with integrated RC-, 32-kHz crystal- and 4-MHz crystal oscillators. Table 2 provides an overview of the available variants. MARC4 Architecture General Description The MARC4 microcontroller consists of an advanced stack-based, 4-bit CPU core and on-chip peripherals. The CPU is based on the HARVARD architecture with physically separate program memory (ROM) and data memory (RAM). Three independent buses, the instruction bus, the memory bus and the I/O bus, are used for parallel communica- tion between ROM, RAM and peripherals. This enhances program execution speed by allowing both instruction prefetching, and a simultaneous communication to the on-chip peripheral circuitry. The extremely powerful integrated interrupt controller with associ- ated eight prioritized interrupt levels supports fast and efficient processing of hardware events. The MARC4 is designed for the high-level programming language qFORTH. The core includes both an expression and a return stack. This architecture enables high-level language programming without any loss of efficiency or code density. Figure 3. MARC4 Core Table 1. Available Variants of ATAxx9x Version Type ROM E2PROM Peripheral Packages Flash device ATAM893 4-Kbyte EEPROM 64 byte SSO20 Production ATAR090 2-Kbyte mask ROM – SSO20 Production ATAR890 2-Kbyte mask ROM 64 byte SSO20 Instruction decoder CCR TOS ALU RAM RP X Y Program 256 x 4-bit MARC4 CORE Clock Reset Sleep Memory bus I/O bus Instruction bus Reset System clock Interrupt controller On-chip peripheral modules memory SP PC |
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