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EP1AGX35EF780C6N Datasheet(PDF) 10 Page - Altera Corporation |
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EP1AGX35EF780C6N Datasheet(HTML) 10 Page - Altera Corporation |
10 / 296 page 2–2 Altera Corporation Arria GX Device Handbook, Volume 1 May 2008 Transceivers Figure 2–1 shows a high-level diagram of the transceiver block architecture divided into four channels. Figure 2–1. Transceiver Block Each transceiver block has: ■ Four transceiver channels with dedicated physical coding sublayer (PCS) and physical media attachment (PMA) circuitry ■ One transmitter PLL that takes in a reference clock and generates high-speed serial clock depending on the functional mode ■ Four receiver PLLs and clock recovery unit (CRU) to recover clock and data from the received serial data stream ■ State machines and other logic to implement special features required to support each protocol Channel 1 Channel 0 Channel 2 Supporting Blocks (PLLs, State Machines, Programming) Channel 3 RX1 TX1 RX0 TX0 RX2 TX2 RX3 TX3 REFCLK_1 REFCLK_0 Transceiver Block Arria GX Logic Array |
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