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SN65LVELT22DR Datasheet(PDF) 1 Page - Texas Instruments |
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SN65LVELT22DR Datasheet(HTML) 1 Page - Texas Instruments |
1 / 10 page 1 FEATURES APPLICATIONS DESCRIPTION PINOUT ASSIGNMENT 1 8 2 7 6 4 5 V CC GND Q 0 Q 0 Q 1 Q 1 D 0 D 1 SN65LVELT22 www.ti.com............................................................................................................................................................................................ SLLS928 – DECEMBER 2008 3.3 V Dual LVTTL to DIfferential LVPECL Translator • Data and Clock Transmission Over Backplane • 450 ps (typ) Propagation Delay • Signaling Level Conversion for Clock or Data • Operating Range: V CC 3.0 V to 3.8 with GND = 0 V • <50 ps (max) Output to Output Skew • Built-in Temperature Compensation • Drop in Compatible to MC100LVELT22 The SN65ELT22 is a dual LVTTL to differential LVPECL translator buffer. It operates on +3V supply and ground only. The output is driven default high when the inputs are left floating or unused. The low output skew makes the device the ideal solution for clock or data signal translation. The SN65LVELT22 is housed in an industry standard SOIC-8 package and is also available in TSSOP-8 package option. Table 1. Pin Description PIN FUNCTION D0, D1 TTL inputs Q0, Q0, Q1, Q1 PECL/ECL outputs VCC Positive supply GND Ground ORDERING INFORMATION(1) PART NUMBER PART MARKING PACKAGE LEAD FINISH SN65LVELT22D SN65LVELT22 SOIC NiPdAu SN65LVELT22DGK SN65LVELT22 SOIC-TSSOP NiPdAu (1) Leaded device options not initially available. Contact TI sales representative for further details. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 2008, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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