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TSS463B Datasheet(PDF) 7 Page - ATMEL Corporation

Part # TSS463B
Description  VAN Data Link Controller with Serial Interface
Download  59 Pages
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

TSS463B Datasheet(HTML) 7 Page - ATMEL Corporation

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TSS463B
4102E–AUTO–12/04
Figure 4. CPOL and CPHA in the TSS463B
At the beginning of a transmission over the serial interface, the first byte is the address
of the TSS463B register to be accessed. The next byte transmitted is the control byte
that determines the direction of the communication. The following bytes are data bytes
(consecutive bytes are written in or read from Address, Address + 1, Address + 2, ...,
Address + n with n = 0 to 28).
To make sure the TSS463B is not out of synchronization, the SPI interface will transmit
data ’0xAA’and ’0x55’on the MISO pin during address and control byte time. This way,
the master always ensures the TSS463B is well-synchronized. If the TSS463B is out of
synchronization, the master can assert the SS pin inactive to resynchronize the SPI
interface or can assert the RESET pin active or can send an initialization sequence.
When the SS pin is inactive, the SCLK is allowed to toggle. This will have no effect on
the TSS463B SPI module.
SPI Control Byte
The SPI control byte is transmitted by the master (CPU) to the TSS463B. It specifies
whether it is a TSS463B Write or Read.
Table 1. SPI Control Byte
DIR: Serial Transfer Direction
Zero: Read Operation. The data bytes will be read by the master (CPU) from the
TSS463B.
One: Write Operation. The data bytes will be written by the master (CPU) to the
TSS463B.
In both cases, address auto-increment mechanism will take place when more than one
data byte is read or written. This mechanism is inhibited when address value reaches
0xFF.
The seven following bits are reserved and must be equal to: 1100000.
When the master (CPU) conducts a write, it sends an address byte, a control byte and
data bytes on its MOSI line. The slave device (TSS463B) will send, if well-synchronized,
’0xAA’during the address byte and ’0x55’during the control byte on its MISO line.
0x55
SCLK
MOSI
SS
SPI 8 Pulses
Data Transmit Points
Data Sample Points
CPOL = CPHA = 1
MISO
0x66
7654321
0
DIR
110000
0


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