7

FN6538.2

December 2, 2008

.

From t1, there is a nominal 4ms delay, which allows the VCC

pin to rise. At the same time, the LGATE/OCSET pin is

will represent the OCSET trip point for the OCP sample and

hold operation. The sample and hold uses a digital counter and

DAC (to save the voltage so the stored value does not degrade)

Protection (OCP)” on page 8 for more details on the equations

and variables. Upon the completion of sample and hold at t2,

the soft-start operation is initiated (around 0.8ms delay to t3),

and then around 4ms for the output voltage to ramp up (0% to

100%) between t3 and t4. The PGOOD output is allowed to go

window.

Soft-Start and Pre-Biased Outputs

Functionally, the soft-start internally ramps the reference on the

non-inverting terminal of the error amp from zero to 0.8V in a

nominal 4ms. The output voltage will thus follow the ramp, from

zero to final value, in the same 4ms. The ramp is created

digitally, so there will be small discrete steps. There is no simple

way to change this ramp rate externally, as it is fixed by the

300kHz (or 600kHz) switching frequency (and the ramp and

delay time is the same for both frequencies).

After an initialization period (t2 to t3), the error amplifier

(COMP/EN pin) is enabled, and begins to regulate the

converter’s output voltage during soft-start. The oscillator’s

triangular waveform is compared to the ramping error amplifier

voltage. This generates PHASE pulses of increasing width that

charge the output capacitors. When the internally generated

soft-start voltage exceeds the reference voltage (0.8V), the

soft-start is complete, and the output should be in regulation at

the expected voltage. This method provides a rapid and

controlled output voltage rise; there is no large in-rush current

charging the output capacitors. The entire start-up sequence

from POR typically takes 9ms; 5ms for the delay and OCP

sample, and 4ms for the soft-start ramp.

begins at t0, and the output ramps between t1 and t2. If the

output is pre-biased to a voltage less than the expected

value (as shown by the magenta curve), the ISL6341x will

detect that condition. Neither MOSFET will turn-on until the

seamlessly ramping from there.

There is a restriction for the pre-bias case; if the pre-biased

discharged, and will not be able to restart. For example, if

5V, then the voltage left on the boot cap (to UGATE) will not

be able to turn on the upper FET. The simple solution here is

If the output is pre-biased to a voltage above the expected

value (as in the red curve), neither MOSFET will turn-on until

the end of the soft-start, at which time it will pull the output

voltage quickly down to the final value. Any resistive load

connected to the output will help pull-down the voltage (at

the RC rate of the R of the load and the C of the output

capacitance).

One exception to the overcharged case is if the pre-bias is

high enough to trip OV protection (>1V on VOS); then

the boot diode) is from a different supply that comes up after

voltage ramp. Once the undervoltage protection is enabled

(at the end of the soft-start ramp), the output will latch off.

alternative is add sequencing logic to the COMP/EN pin to

(see “Input Voltage Considerations” on page 12).

LGATE

STARTS

SWITCHING

4.0ms

(0.25V/DIV)

GND>

GND>

GND>

GND>

t0

t1

t2

t3

t4

0.8ms

4.0ms

COMP/EN (0.25V/DIV)

0.25V/DIV

LGATE/OCSET

0.7V

PGOOD (2V/DIV)

FIGURE 2. LGATE/OCSET AND SOFT-START OPERATION

FIGURE 3. SOFT-START WITH PRE-BIAS

GND>

GND>

GND>

t0

t1

t2

ISL6341, ISL6341A, ISL6341B, ISL6341C