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AT87C5103-IBSAL Datasheet(PDF) 9 Page - ATMEL Corporation |
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AT87C5103-IBSAL Datasheet(HTML) 9 Page - ATMEL Corporation |
9 / 64 page 9 4134D–8051–02/08 Table 2. CKCON1 Register CKCON1 (S:AFh) Clock Control Register Note: 1. This control bit is validated when the CPU clock bit X2 is set; when X2 is low, this bit has no effect. Reset Value = XXXX XXX0b 7 6 5 4 3 2 1 0 SPIX2 Bit Number Bit Mnemonic Description 7 – Reserved The value read from this bit is indeterminate. Do not set this bit. 6 – Reserved The value read from this bit is indeterminate. Do not set this bit. 5 – Reserved The value read from this bit is indeterminate. Do not set this bit. 4 – Reserved The value read from this bit is indeterminate. Do not set this bit. 3 – Reserved The value read from this bit is indeterminate. Do not set this bit. 2 – Reserved The value read from this bit is indeterminate. Do not set this bit. 1 – Reserved The value read from this bit is indeterminate. Do not set this bit. 0 SPIX2 SPI clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. |
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