AT80C51RD2-3CSCM datasheet(5/86 Pages) ATMEL

Part #	AT80C51RD2-3CSCM

Description	80C51 High Performance ROM 8-bit Microcontroller

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Manufacturer	ATMEL [ATMEL Corporation]

Direct Link	http://www.atmel.com

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5

4113C–8051–01/08

AT8xc51Rx2

P2.0 - P2.7

21 - 28

24 - 31

18 - 25

I/O

Port 2: Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. Port 2 pins

that have 1s written to them are pulled high by the internal pull-ups and can be

used as inputs. As inputs, Port 2 pins that are externally pulled low will source

current because of the internal pull-ups. Port 2 emits the high-order address byte

during fetches from external program memory and during accesses to external

data memory that use 16-bit addresses (MOVX @DPTR). In this application, it

uses strong internal pull-ups emitting 1s. During accesses to external data memory

that use 8-bit addresses (MOVX @Ri), Port 2 emits the contents of the P2 SFR.

Some Port 2 pins receive the high order address bits during ROM reading and

verification:

P2.0 to P2.5 for 16 KB devices

P2.0 to P2.6 for 32 KB devices

P3.0 - P3.7

10 - 17

11,

13 - 19

5,

7 - 13

I/O

Port 3: Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. Port 3 pins

that have 1s written to them are pulled high by the internal pull-ups and can be

used as inputs. As inputs, Port 3 pins that are externally pulled low will source

current because of the internal pull-ups. Port 3 also serves the special features of

the 80C51 family, as listed below.

10

11

5

I

RXD (P3.0): Serial input port

11

13

7

O

TXD (P3.1): Serial output port

12

14

8

I

INT0 (P3.2): External interrupt 0

13

15

9

I

INT1 (P3.3): External interrupt 1

14

16

10

I

T0 (P3.4): Timer 0 external input

15

17

11

I

T1 (P3.5): Timer 1 external input

16

18

12

O

WR (P3.6): External data memory write strobe

17

19

13

O

RD (P3.7): External data memory read strobe

RST

9

10

4

I/O

Reset: A high on this pin for two machine cycles while the oscillator is running,

resets the device. An internal diffused resistor to VSS permits a power-on reset

using only an external capacitor to V

CC. This pin is an output when the hardware

watchdog forces a system reset.

ALE/PROG

30

33

27

O (I)

Address Latch Enable/Program Pulse: Output pulse for latching the low byte of

the address during an access to external memory. In normal operation, ALE is

emitted at a constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can

be used for external timing or clocking. Note that one ALE pulse is skipped during

each access to external data memory. This pin is also the program pulse input

(PROG) during Flash programming. ALE can be disabled by setting SFR’s AUXR.0

bit. With this bit set, ALE will be inactive during internal fetches.

PSEN

29

32

26

O

Program Strobe Enable: The read strobe to external program memory. When

executing code from the external program memory, PSEN is activated twice each

machine cycle, except that two PSEN activations are skipped during each access

to external data memory. PSEN is not activated during fetches from internal

program memory.

EA

31

35

29

I

External Access Enable: EA must be externally held low to enable the device to

fetch code from external program memory locations 0000H to 3FFFH (16K),

7FFFH (32K). If security level 1 is programmed, EA will be internally latched on

Reset.

Table 3-1.

Pin Description (Continued)

Mnemonic

Pin Number

Type

Name and Function

DIL

PLCC44

VQFP44 1.4

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AT80C51RD2-3CSCM Datasheet(PDF) 5 Page - ATMEL Corporation

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