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SA12 Datasheet(PDF) 4 Page - Cirrus Logic |
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SA12 Datasheet(HTML) 4 Page - Cirrus Logic |
4 / 4 page APEX MICROTECHNOLOGY CORPORATION • 5980 NORTH SHANNON ROAD • TUCSON, ARIZONA 85741 • USA • APPLICATIONS HOTLINE: 1 (800) 546-2739 4 Switching noise spikes will in- variably be found at the I SENSE pins. The noise spikes could trip the current limit threshold which is only 100 mV. R FILTER and CFILTER should be adjusted so as to reduce the switching noise well below 100 mV to prevent false current limiting. The sum of the DC level plus the noise peak will determine the current limiting value. As in most switching circuits it may be dif- ficult to determine the true noise amplitude without careful attention to grounding of the oscilloscope probe. Use the shortest possible ground lead for the probe and connect exactly at the GND terminal of the amplifier. Suggested starting values are C FILTER = .01uF, R FILTER = 5k . The required value of R LIMIT in voltage mode may be cal- culated by: R LIMIT = .1 V / ILIMIT where R LIMIT is the required resistor value, and ILIMIT is the maximum desired current. In current mode the required value of each R LIMIT is 2 times this value since the sense voltage is divided down by 2 (see Figure B). If R SHDN is used it will further divide down the sense voltage. The shutdown divider network will also have an effect on the filtering circuit. BYPASSING Adequate bypassing of the power supplies is required for proper operation. Failure to do so can cause erratic and low efficiency operation as well as excessive ringing at the out- puts. The Vs supply should be bypassed with at least a 1µF ceramic capacitor in parallel with another low ESR capacitor of at least 10µF per amp of output current. Capacitor types rated for switching applications are the only types that should be considered. The bypass capacitors must be physically connected directly to the power supply pins. Even one inch of lead length will cause excessive ringing at the outputs. This is due to the very fast switching times and the inductance of the lead connection. The bypassing requirements of the Vcc supply are less stringent, but still necessary. A .1µF to .47µF ceramic capacitor connected directly to the Vcc pin will suffice. MODULATION RANGE The high side of the all N channel H-bridge is driven by a bootstrap circuit. For the output circuit to switch high, the low side circuit must have previously been switched on in order to charge the bootstrap capacitor. Therefore, if the input signal to the SA12 demands a 100% duty cycle upon start-up the output will not follow and will be in a tri-state (open) condition. The ramp signal must cross the input signal at some point to cor- rectly determine the output state. After the ramp crosses the input signal one time the output state will be correct thereafter. In addition, if during normal operation the input signal drives the SA12 beyond its linear modulation range (approximately 95%) the output will jump to 100% modulation. GENERAL Please read Application Note 30 on "PWM Basics". Refer to Application Note 1 "General Operating Considerations" for helpful information regarding power supplies, heat sinking and mounting. Visit www.apexmicrotech.com for design tools that help automate pwm filter design; heat sink selection; Apex’s complete Application Notes library; Technical Seminar Work- book; and Evaluation Kits. CLOCK CIRCUIT AND RAMP GENERATOR The clock frequency is internally set to a frequency of ap- proximately 400kHz. The CLK OUT pin will normally be tied to the CLK IN pin. The clock is divided by two and applied to an RC network which produces a ramp signal at the –PWM/RAMP pin. An external clock signal can be applied to the CLK IN pin for synchronization purposes. If a clock frequency lower than 400kHz is chosen an external capacitor must be tied to the –PWM/RAMP pin. This capacitor, which parallels an internal capacitor, must be selected so that the ramp oscillates 4 volts p-p with the lower peak 3 volts above ground. PWM INPUTS The full bridge driver may be accessed via the pwm input comparator. When +PWM > -PWM then A OUT > B OUT. A motion control processor which generates the pwm signal can drive these pins with signals referenced to GND. PROTECTION CIRCUITS A fixed internal current limit senses the high side current. Should either of the outputs be shorted to ground the high side current limit will latch off the output transistors. The tem- perature of the output transistors is also monitored. Should a fault condition raise the temperature of the output transistors to 165°C the thermal protection circuit will latch off the output transistors. The latched condition can be cleared by either recycling the V cc power or by toggling the I LIMIT/SHDN input with a 10V pulse. See Figures A and B. The outputs will remain off as long as the shutdown pulse is high (10V). When supply voltage is over 100V, these circuits may not protect the FET switches in the case of short circuits directly at the pins of the amplifier. However, a small inductance be- tween the amplifier and the short circuit will limit current rise time and the protection circuits will be effective. A pair of 12 inch wires is adequate inductance. CURRENT LIMIT There are two load current sensing pins, I SENSE A and I SENSE B. The two pins can be shorted in the voltage mode connection but both must be used in the current modeconnection(seefigures A and B). It is recommended that R LIMIT resistors be non-in- ductive. Load current flows in the I SENSE pins. To avoid errors due to lead lengths connect the I LIMIT/SHDN pin directly to the R LIMIT resistors (through the filter network and shutdown divider resistor) and connect the R LIMIT resistors directly to the GND pin. OPERATING CONSIDERATIONS SA12 This data sheet has been carefully checked and is believed to be reliable, however, no responsibility is assumed for possible inaccuracies or omissions. All specifications are subject to change without notice. SA12U REV G AUGUST 2007 © 2007 Apex Microtechnology Corp. |
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