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AT26F004-SSU Datasheet(PDF) 2 Page - ATMEL Corporation |
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AT26F004-SSU Datasheet(HTML) 2 Page - ATMEL Corporation |
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2 / 38 page  2 3588D–DFLASH–10/08 AT26F004 The AT26F004 also offers a sophisticated method for protecting individual sectors against erroneous or malicious program and erase operations. By providing the ability to individually protect and unprotect sectors, a system can unprotect a specific sector to modify its contents while keeping the remaining sectors of the memory array securely protected. This is useful in applications where program code is patched or updated on a subroutine or module basis, or in applications where data storage segments need to be modified without running the risk of errant modifications to the program code segments. Specifically designed for use in 3-volt systems, the AT26F004 supports read, program, and erase operations with a supply voltage range of 2.7V to 3.6V. No separate voltage is required for programming and erasing. 2. Pin Descriptions and Pinouts Table 2-1. Pin Descriptions Symbol Name and Function Asserted State Type CS CHIP SELECT: Asserting the CS pin selects the device. When the CS pin is deasserted, the device will be deselected and normally placed in standby mode (not Deep Power-down mode), and the SO pin will be in a high-impedance state. When the device is deselected, data will not be accepted on the SI pin. A high-to-low transition on the CS pin is required to start an operation, and a low-to-high transition is required to end an operation. When ending an internally self-timed operation such as a program or erase cycle, the device will not enter the standby mode until the completion of the operation. Low Input SCK SERIAL CLOCK: This pin is used to provide a clock to the device and is used to control the flow of data to and from the device. Command, address, and input data present on the SI pin is always latched on the rising edge of SCK, while output data on the SO pin is always clocked out on the falling edge of SCK. – Input SI SERIAL INPUT: The SI pin is used to shift data into the device. The SI pin is used for all data input including command and address sequences. Data on the SI pin is always latched on the rising edge of SCK. – Input SO SERIAL OUTPUT: The SO pin is used to shift data out from the device. Data on the SO pin is always clocked out on the falling edge of SCK. – Output WP WRITE PROTECT: The WP pin controls the hardware locking feature of the device. Refer to section “Protection Commands and Features” on page 13 for more details on protection features and the WP pin. The WP pin is not internally pulled-high and cannot be left floating. If hardware controlled locking will not be used, then the WP pin must be externally connected to V CC. Low Input HOLD HOLD: The HOLD pin is used to temporarily pause serial communication without deselecting or resetting the device. While the HOLD pin is asserted, transitions on the SCK pin and data on the SI pin will be ignored, and the SO pin will be in a high-impedance state. The CS pin must be asserted, and the SCK pin must be in the low state in order for a Hold condition to start. A Hold condition pauses serial communication only and does not have an effect on internally self-timed operations such as a program or erase cycle. Please refer to section “Hold” on page 27 for additional details on the Hold operation. The HOLD pin is not internally pulled-high and cannot be left floating. If the Hold function will not be used, then the HOLD pin must be externally connected to VCC. Low Input VCC DEVICE POWER SUPPLY: The V CC pin is used to supply the source voltage to the device. Operations at invalid VCC voltages may produce spurious results and should not be attempted. –Power GND GROUND: The ground reference for the power supply. GND should be connected to the system ground. –Power |
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