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3492A–PLD–12/05

ATF1502BE

Figure 1-2.

Block Diagram

Each of the 32 macrocells generates a buried feedback signal that goes to the global bus (see

Figure 1-2). Each input and I/O pin also feeds into the global bus. The switch matrix in each logic

block then selects 40 individual signals from the global bus. Each macrocell also generates a

foldback logic term that goes to a regional bus. Cascade logic between macrocells in the

ATF1502BE allows fast, efficient generation of complex logic functions. The ATF1502BE con-

tains four such logic chains, each capable of creating sum term logic with a fan-in of up to 40

product terms.

The ATF1502BE macrocell, shown in Figure 1-3, is flexible enough to support highly complex

logic functions operating at high speed. The macrocell consists of five sections: product terms

and product term select multiplexer, OR/XOR/CASCADE logic, a flip-flop, output select and

enable, and logic array inputs.

A security fuse, when programmed, protects the contents of the ATF1502BE. Two bytes

(16 bits) of User Signature are accessible to the user for purposes such as storing project name,

part number, revision or date. The User Signature is accessible regardless of the state of the

security fuse.

The ATF1502BE device is an In-System Programming (ISP) device. It uses the industry-stan-

dard 4-pin JTAG interface (IEEE Std. 1149.1), and is fully compliant with JTAG’s Boundary-scan

Description Language (BSDL). ISP allows the device to be programmed without removing it from

the printed circuit board. In addition to simplifying the manufacturing flow, ISP also allows design

modifications to be made in the field via software.

B

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