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AT94S40AL-25DGI Datasheet(PDF) 6 Page - ATMEL Corporation |
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AT94S40AL-25DGI Datasheet(HTML) 6 Page - ATMEL Corporation |
6 / 32 page 6 2314E–FPSLI–6/05 AT94S Secure Family 4.5 Acknowledge Bit The Acknowledge (ACK) Bit shown in Figure 4-1 is provided by the Configurator receiving the byte. The receiving Configurator can accept the byte by asserting a Low value on the cSDA line, or it can refuse the byte by asserting (allowing the signal to be externally pulled up to) a High value on the cSDA line. All bytes from accepted messages must be terminated by either an Acknowledge Bit or a Stop Condition. Following an ACK Bit, when the cSDA line is released dur- ing an exchange of control between the Configurator and the programmer, the cSDA line may be pulled High temporarily due to the open-collector output nature of the line. Control of the line must resume before the next rising edge of the clock. 4.6 Bit Ordering Protocol The most significant bit is the first bit of a byte transmitted on the cSDA line for the Device Address Byte and the EEPROM Address Bytes. It is followed by the lesser significant bits until the eighth bit, the least significant bit, is transmitted. However, for Data Bytes (both writing and reading), the first bit transmitted is the least significant bit. This protocol is shown in the diagrams below. 4.7 Device Address Byte The contents of the Device Address Byte are shown below, along with the order in which the bits are clocked into the device. The CE pin cannot be used for device selection in programming mode (i.e., when SER_EN is drive Low). Figure 4-1. Start and Stop Conditions Where:R/W=1 Read = 0 Write 8th Bit STOP Condition Byte n cSCK cSDA START Condition tWR ACK BIT Table 4-1. Device Address Byte MSB LSB 1010011 R/W 1st 2nd 3rd 4th 5th 6th 7th 8th |
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