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AT94S05AL-25DGC Datasheet(PDF) 5 Page - ATMEL Corporation |
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AT94S05AL-25DGC Datasheet(HTML) 5 Page - ATMEL Corporation |
5 / 32 page 5 2314E–FPSLI–6/05 AT94S Secure Family may only drive the cSDA line Low. The system must provide a small pull-up current (1 k Ω equiv- alent) for the cSDA line. The MESSAGE FORMAT for read and write instructions consists of the bytes shown in “Bit For- mat” on page 5. While writing, the programmer is responsible for issuing the instruction and data. While reading, the programmer issues the instruction and acknowledges the data from the Configurator as necessary. Again, the Acknowledge Bit is asserted on the cSDA line by the receiving device on a byte-by- byte basis. The factory blanks devices to all zeros before shipping. The array cannot otherwise be “initial- ized” except by explicitly writing a known value to each location using the serial protocol described herein. 4.3 Bit Format Data on the cSDA pin may change only during the cSCK Low time; whereas Start and Stop Con- ditions are identified as transitions during the cSCK High time. Write Instruction Message Format Current Address Read (Extended to Sequential Read) Instruction Message Format 4.4 Start and Stop Conditions The Start Condition is indicated by a high-to-low transition of the cSDA line when the cSCK line is High. Similarly, the Stop Condition is generated by a low-to-high transition of the cSDA line when the cSCK line is High, as shown in Figure 4-1. The Start Condition will return the device to the state where it is waiting for a Device Address (its normal quiescent mode). The Stop Condition initiates an internally timed write signal whose maximum duration is t WR (refer to AC Characteristics table for actual value). During this time, the Configurator must remain in programming mode (i.e., SER_EN is driven Low). cSDA and cSCK lines are ignored until the cycle is completed. Since the write cycle typically completes in less than t WR seconds, we recommend the use of “polling” as described in later sections. Input levels to all other pins should be held constant until the write cycle has been completed. ACK BIT (CONFIGURATOR) DATA BYTE n STOP CONDITION START CONDITION DEVICE ADDRESS MS EEPROM ADDRESS BYTE (NEXT) EEPROM ADDRESS BYTE LS EEPROM ADDRESS BYTE DATA BYTE 1 ACK BIT (CONFIGURATOR) DATA BYTE n STOP CONDITION START CONDITION DEVICE ADDRESS DATA BYTE 1 ACK BIT (PROGRAMMER) |
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