11

0776L–PLD–11/08

ATF750C(L)

21. Power-up Reset

The registers in the ATF750C(L)s are designed to reset during power-up. At a point delayed

slightly from V

depend on the polarity of the output buffer.

This feature is critical for state machine initialization. However, due to the asynchronous nature

of reset and the uncertainty of how V

required:

1.

The V

2.

After reset occurs, all input and feedback setup times must be met before driving the

clock terms or pin high, and

3.

The clock pin, or signals from which clock terms are derived, must remain stable

during t

22. Pin Capacitance

Note:

1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100%

tested.

Parameter

Description

Typ

Max

Units

Power-up Reset Time

600

1000

ns

V

RST

Power-up Reset Voltage

2.0

4.5

V

f = 1 MHz, T = 25°C

(1)

Typ

Max

Units

Conditions

58

pF

C

OUT

68

pF

V