2

0776L–PLD–11/08

ATF750C(L)

3.

Description

The ATF750C(L)s are twice as powerful as most other 24-pin programmable logic devices.

Increased product terms, sum terms, flip-flops and output logic configurations

translate into more usable gates. High-speed logic and uniform predictable delays guarantee

fast in-system performance. The ATF750C(L) is a high-performance CMOS (electrically-eras-

able) complex programmable logic device (CPLD) that utilizes Atmel’s proven electrically-

erasable technology.

Each of the ATF750C(L)’s 22 logic pins can be used as an input. Ten of these can be used as

inputs, outputs or bi-directional I/O pins. Each flip-flop is individually configurable as either D- or

T-type. Each flip-flop output is fed back into the array independently. This allows burying of all

the sum terms and flip-flops.

There are 171 total product terms available. There are two sum terms per output, providing

added flexibility. A variable format is used to assign between four to eight product terms per sum

term. Much more logic can be replaced by this device than by any other 24-pin PLD. With 20

sum terms and flip-flops, complex state machines are easily implemented with logic to spare.

Product terms provide individual clocks and asynchronous resets for each flip-flop. Each flip-flop

may also be individually configured to have direct input pin controlled clocking. Each output has

its own enable product term. One product term provides a common synchronous preset for all

flip-flops. Register preload functions are provided to simplify testing. All registers automatically

reset upon power-up.

The ATF750CL is a low-power device with speeds as fast as 15 ns. The ATF750CL provides the

optimum low-power CPLD solution. This device significantly reduces total system power,

thereby allowing battery-powered operations.

2.

Pin Configurations

Pin

Function

CLK

Clock

IN

Logic Inputs

I/O

Bi-directional Buffers

GND

Ground

VCC

+5V Supply

2.1

DIP/SOIC/TSSOP

2.2

PLCC/LCC

Note:

For PLCC, pins 1, 8, 15, and 22 can be left uncon-

nected. For superior performance, connect VCC to pin 1

and GND to pins 8, 15, and 22.

1

2

3

4

5

6

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

CLK/IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

GND

VCC

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

IN

5

6

7

8

9

10

11

25

24

23

22

21

20

19

IN

IN

IN

IN

IN

IN

I/O

I/O

I/O

I/O

I/O

I/O