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ATF22V10CZ-15JC Datasheet(PDF) 6 Page - ATMEL Corporation |
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ATF22V10CZ-15JC Datasheet(HTML) 6 Page - ATMEL Corporation |
6 / 20 page 6 0778J–PLD–11/07 ATF22V10C(Q)Z 4.4 Input Test Waveforms 4.4.1 Input Test Waveforms and Measurement Levels 4.4.2 Output Test Loads Note: Similar competitors devices are specified with slightly different loads. These load differences may affect output signals’ delay and slew rate. Atmel devices are tested with sufficient margins to meet compatible device specification conditions. 4.5 Pin Capacitance Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. 4.6 Power-up Reset The registers in the ATF22V10CZ/CQZ are designed to reset during power-up. At a point delayed slightly from V CC crossing VRST, all registers will be reset to the low state. The output state will depend on the polarity of the buffer. This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the uncertainty of how V CC actually rises in the system, the following conditions are required: 1. The V CC rise must be monotonic and start below 0.7V. 2. The clock must remain stable during T PR. 3. After T PR occurs, all input and feedback setup times must be met before driving the clock pin high. 4.7 Preload of Register Outputs The ATF22V10CZ/CQZ’s registers are provided with circuitry to allow loading of each register with either a high or a low. This feature will simplify testing since any state can be forced into the registers to control test sequencing. A JEDEC file with preload is generated when a source file Table 4-1. Pin Capacitance (f = 1 MHz, T = 25C(1)) Typ Max Units Conditions C IN 810 pF V IN = 0V; f = 1.0 MHz C I/O 810 pF V OUT = 0V; f = 1.0 MHz |
Similar Part No. - ATF22V10CZ-15JC |
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Similar Description - ATF22V10CZ-15JC |
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