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AT27C2048-90JU Datasheet(PDF) 3 Page - ATMEL Corporation |
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AT27C2048-90JU Datasheet(HTML) 3 Page - ATMEL Corporation |
3 / 14 page 3 0632F–EPROM–12/07 AT27C2048 3. System Considerations Switching between active and standby conditions via the Chip Enable pin may produce transient voltage excursions. Unless accommodated by the system design, these transients may exceed datasheet limits, resulting in device non-conformance. At a minimum, a 0.1 µF high frequency, low inherent inductance, ceramic capacitor should be utilized for each device. This capacitor should be connected between the V CC and Ground terminals of the device, as close to the device as possible. Additionally, to stabilize the supply voltage level on printed circuit boards with large EPROM arrays, a 4.7 µF bulk electrolytic capacitor should be utilized, again con- nected between the V CC and Ground terminals. This capacitor should be positioned as close as possible to the point where the power supply is connected to the array. 4. Block Diagram Note: 1. Maximum voltage is -0.6V DC which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is V CC + 0.75V DC which may overshoot to +7.0V for pulses of less than 20 ns. 5. Absolute Maximum Ratings* Temperature Under Bias............................... -55 ° C to +125° C Storage Temperature .................................... -65 ° C to +150° C Voltage on Any Pin with Respect to Ground .........................................-2.0V to +7.0V(1) Voltage on A9 with Respect to Ground ......................................-2.0V to +14.0V(1) VPP Supply Voltage with Respect to Ground .......................................-2.0V to +14.0V(1) *NOTICE: Stresses beyond those listed under “Absolute Maxi- mum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condi- tions beyond those indicated in the operational sec- tions of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. GND VPP VCC DATA OUTPUTS O0 - O15 OE, CE AND PROGRAM LOGIC Y DECODER X DECODER OUTPUT BUFFERS Y-GATING CELL MATRIX IDENTIFICATION A0 - A17 ADDRESS INPUTS OE CE |
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