AT32AP7001 datasheet(6/49 Pages) ATMEL

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AT32AP7001 Datasheet(PDF) 6 Page - ATMEL Corporation

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32015ES–AVR32–01/08

AT32AP7001

– Round-Robin Arbitration (three modes supported: no default master, last

accessed default

master, fixed default master)

– Burst Breaking with Slot Cycle Limit

– One Address Decoder Provided per Master

• 2 Peripheral buses allowing each bus to run on different bus speeds.

– PB A intended to run on low clock speeds, with peripherals connected to the PDC.

– PB B intended to run on higher clock speeds, with peripherals connected to the DMACA.

• HSB-HSB Bridge providing a low-speed HSB bus running at the same speed as PBA

– Allows PDC transfers between a low-speed PB bus and a bus matrix of higher clock speeds

An overview of the bus system is given in Figure 4-1 on page 13. All modules connected to the

same bus use the same clock, but the clock to each module can be individually shut off by the

Power Manager. The figure identifies the number of master and slave interfaces of each module

connected to the HSB bus, and which DMA controller is connected to which peripheral.

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