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AT91CAP9SC250A-CJ Datasheet(PDF) 1 Page - ATMEL Corporation |
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AT91CAP9SC250A-CJ Datasheet(HTML) 1 Page - ATMEL Corporation |
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1 / 60 page  NOTE: This is a summary document. The complete document is available under NDA. Please contact an Atmel Sales Representative. www.atmel.com/contacts/ Features • Incorporates the ARM926EJ-S™ ARM® Thumb® Processor – DSP Instruction Extensions, ARM Jazelle® Technology for Java® Acceleration – 16 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer – 220 MIPS at 200 MHz – Memory Management Unit – EmbeddedICE™ In-circuit Emulation, Debug Communication Channel Support • Additional Embedded Memories – One 32 Kbyte Internal ROM, Single-cycle Access at Maximum Matrix Speed – One 32 Kbyte Internal SRAM, Single-cycle Access at Maximum Matrix Speed • External Bus Interface (EBI) – EBI Supports Mobile DDR, SDRAM, Low Power SDRAM, Static Memory, Synchronous CellularRAM, ECC-enabled NAND Flash and CompactFlash® • Metal Programmable (MP) Block – 500,000 Gates/250,000 Gates Metal Programmable Logic (through 5 Metal Layers) for AT91CAP9SC500A/AT91CAP9SC250A Respectively – Ten 512 x 36-bit Dual Port RAMs – Eight 512 x 72-bit Single Port RAMs – High Connectivity for Up to Three AHB Masters and Four AHB Slaves – Up to Seven AIC Interrupt Inputs – Up to Four DMA Hardware Handshake Interfaces – Delay Lines for Double Data Rate Interface – UTMI+ Full Connection – Up to 77 Dedicated I/Os • LCD Controller – Supports Passive or Active Displays – Up to 24 Bits per Pixel in TFT Mode, Up to 16 Bits per Pixel in STN Color Mode – Up to 16M Colors in TFT Mode, Resolution Up to 2048x2048, Supports Wider Screen Buffers • Image Sensor Interface – ITU-R BT. 601/656 External Interface, Programmable Frame Capture Rate – 12-bit Data Interface for Support of High Sensibility Sensors – SAV and EAV Synchronization, Preview Path with Scaler, YCbCr Format • USB 2.0 Full Speed (12 Mbits per second) OHCI Host Double Port – Dual On-chip Transceivers – Integrated FIFOs and Dedicated DMA Channels • USB 2.0 High Speed (480 Mbits per second) Device Port – On-chip Transceiver, 4 Kbyte Configurable Integrated DPRAM – Integrated FIFOs and Dedicated DMA Channels – Integrated UTMI+ Physical Interface • Ethernet MAC 10/100 Base T – Media Independent Interface (MII) or Reduced Media Independent Interface (RMII) – 28-byte FIFOs and Dedicated DMA Channels for Receive and Transmit • Multi-Layer Bus Matrix – Twelve 32-bit-layer Matrix, Allowing a Maximum of 38.4 Gbps of On-chip Bus Bandwidth at Maximum 100 MHz System Clock Speed – Boot Mode Select Option, Remap Command • Fully-featured System Controller, Including – Reset Controller, Shutdown Controller 6270AS–CAP–10-Jan-08 Customizable Microcontroller Processor AT91CAP9SC500A AT91CAP9SC250A Summary Preliminary |
Similar Part No. - AT91CAP9SC250A-CJ |
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Similar Description - AT91CAP9SC250A-CJ |
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