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AT91SAM9261S-CJ Datasheet(PDF) 1 Page - ATMEL Corporation |
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AT91SAM9261S-CJ Datasheet(HTML) 1 Page - ATMEL Corporation |
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1 / 39 page  Features • Incorporates the ARM926EJ-S™ ARM® Thumb® Processor – DSP Instruction Extensions – ARM Jazelle® Technology for Java® Acceleration – 16 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer – 210 MIPS at 190 MHz – Memory Management Unit – EmbeddedICE™, Debug Communication Channel Support – Mid-level implementation Embedded Trace Macrocell™ • Additional Embedded Memories – 32 Kbytes of Internal ROM, Single-cycle Access at Maximum Bus Speed – 16 Kbytes of Internal SRAM, Single-cycle Access at Bus Speed • External Bus Interface (EBI) – Supports SDRAM, Static Memory, NAND Flash and CompactFlash® • LCD Controller – Supports Passive or Active Displays – Up to 16-bits per Pixel in STN Color Mode – Up to 16M Colors in TFT Mode (24-bit per Pixel), Resolution up to 2048 x 2048 • USB – USB 2.0 Full Speed (12 Mbits per second) Host Double Port • Dual On-chip Transceivers • Integrated FIFOs and Dedicated DMA Channels – USB 2.0 Full Speed (12 Mbits per second) Device Port • On-chip Transceiver, 2 Kbyte Configurable Integrated FIFOs • Bus Matrix – Handles Five Masters and Five Slaves – Boot Mode Select Option – Remap Command • Fully Featured System Controller (SYSC) for Efficient System Management, including – Reset Controller, Shutdown Controller, Four 32-bit Battery Backup Registers for a Total of 16 Bytes – Clock Generator and Power Management Controller – Advanced Interrupt Controller and Debug Unit – Periodic Interval Timer, Watchdog Timer and Real-time Timer – Three 32-bit PIO Controllers • Reset Controller (RSTC) – Based on Power-on Reset Cells, Reset Source Identification and Reset Output Control • Shutdown Controller (SHDWC) – Programmable Shutdown Pin Control and Wake-up Circuitry • Clock Generator (CKGR) – 32,768 Hz Low-power Oscillator on Battery Backup Power Supply, Providing a Permanent Slow Clock – 3 to 20 MHz On-chip Oscillator and two PLLs • Power Management Controller (PMC) – Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities – Four Programmable External Clock Signals AT91 ARM Thumb-based Microcontrollers AT91SAM9261S Summary 6242DS–ATARM–06-Jan-09 |
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