5

5204AS–CRYPT–7/08

AT88SC0808CA

7.

Device Operations for Synchronous Protocols

7.1

Clock and Data Transitions

The SDA pin is normally pulled high with an external device. Data on the SDA pin may change

only during SCL low time periods (see Figure 7-3 on page 6). Data changes during SCL high

periods will indicate a start or stop condition as defined below.

7.1.1

Start Condition

A high-to-low transition of SDA with SCL high defines a START condition which must precede all

commands (see Figure 7-4 on page 7).

7.1.2

Stop Condition

A low-to-high transition of SDA with SCL high defines a STOP condition. After a read sequence,

the STOP condition will place the EEPROM in a standby power mode (see Figure 7-4 on page

7).

7.1.3

ACKNOWLEDGE

All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words.

The EEPROM sends a zero to acknowledge that it has received each word. This happens dur-

ing the ninth clock cycle (see Figure 7-5 on page 7).

Table 6-2.

AC Characteristics

Applicable over recommended operating range from V

Parameter

Min

Max

Units

f

CLK

Async Clock Frequency

1

4

MHz

f

CLK

Synch Clock Frequency

0

1

MHz

Clock Duty cycle

40

60

%

t

R

“Rise Time - SDA/IO, RST”

1

uS

“Fall Time - SDA/IO, RST”

1

uS

Rise Time - SCL/CLK

9% x period

uS

t

F

Fall Time - SCL/CLK

9% x period

uS

Clock Low to Data Out Valid

250

nS

Start Hold Time

200

nS

t

SU.STA

Start Set-up Time

200

nS

Data In Hold Time

10

nS

Data In Set-up Time

100

nS

t

SU.STO

Stop Set-up Time

200

nS

Data Out Hold Time

20

nS

Write Cycle Time

5mS