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PCA9543C Datasheet(PDF) 8 Page - NXP Semiconductors |
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PCA9543C Datasheet(HTML) 8 Page - NXP Semiconductors |
8 / 23 page PCA9543A_43B_43C_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 17 November 2008 8 of 23 NXP Semiconductors PCA9543A/43B/43C 2-channel I2C-bus switch with interrupt logic and reset Figure 8, we see that Vo(sw)(max) will be at 2.7 V when the PCA9543A supply voltage is 3.5 V or lower, so the PCA9543A supply voltage could be set to 3.3 V. Pull-up resistors can then be used to bring the bus voltages to their appropriate levels (see Figure 15). More Information can be found in Application Note AN262: PCA954X family of I2C/SMBus multiplexers and switches. 7. Characteristics of the I2C-bus The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 7.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure 9). 7.2 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P) (see Figure 10). Fig 9. Bit transfer mba607 data line stable; data valid change of data allowed SDA SCL Fig 10. Definition of START and STOP conditions mba608 SDA SCL P STOP condition SDA SCL S START condition |
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