PCA9541_08 datasheet(2/43 Pages) NXP

Part #	PCA9541

Description	2-to-1 I2C-bus master selector with interrupt logic and reset

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Manufacturer	NXP [NXP Semiconductors]

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PCA9541_6

Product data sheet

Rev. 06 — 11 September 2008

2 of 43

NXP Semiconductors

PCA9541

2-to-1 I2C-bus master selector with interrupt logic and reset

External pull-up resistors pull the bus to the desired voltage level for each channel. All I/O

pins are 6.0 V tolerant.

An active LOW reset input allows the PCA9541 to be initialized. Pulling the RESET pin

LOW resets the I2C-bus state machine and conﬁgures the device to its default state as

does the internal Power-On Reset (POR) function.

The PCA9541/02 version is being discontinued as of December 2007 and customers

should use PCA9541/03.

2.

Features

I 2-to-1 bidirectional master selector

I I2C-bus interface logic; compatible with SMBus standards

I PCA9541/01 powers up with Channel 0 selected

I PCA9541/02 powers up with Channel 0 selected after STOP condition detected (bus

idle) on Channel 0

I PCA9541/03 powers up with no channel selected and either master can take control of

the bus

I Active LOW interrupt input

I 2 active LOW interrupt outputs

I Active LOW reset input

I 4 address pins allowing up to 16 devices on the I2C-bus

I Channel selection via I2C-bus

I Bus initialization/recovery function

I Bus trafﬁc sensor

I Low Ron switches

I Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and 5 V buses

I No glitch on power-up

I Supports hot insertion

I Software identical for both masters

I Low standby current

I Operating power supply voltage range of 2.3 V to 5.5 V

I 6.0 V tolerant inputs

I 0 Hz to 400 kHz clock frequency

I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per

JESD22-A115, and 1000 V CDM per JESD22-C101

I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

I Packages offered: SO16, TSSOP16, HVQFN16

3.

Applications

I High reliability systems with dual masters

I Gatekeeper multiplexer on long single bus

I Bus initialization/recovery for slave devices without hardware reset

I Allows masters without arbitration logic to share resources

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