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ISP1582 Datasheet(PDF) 11 Page - NXP Semiconductors |
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ISP1582 Datasheet(HTML) 11 Page - NXP Semiconductors |
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11 / 69 page  ISP1582_7 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 — 22 September 2008 10 of 68 NXP Semiconductors ISP1582 Hi-Speed USB peripheral controller Any A-device, including a PC or laptop, can respond to SRP. Any B-device, including a standard USB peripheral, can initiate SRP. The ISP1582 is a device that can initiate SRP. 7.6 NXP high-speed transceiver 7.6.1 NXP Parallel Interface Engine (PIE) In the High-Speed (HS) transceiver, the NXP PIE interface uses a 16-bit parallel bidirectional data interface. The functions of the HS module also include bit-stuffing or de-stuffing and Non-Return-to-Zero Inverted (NRZI) encoding or decoding logic. 7.6.2 Peripheral circuit To maintain a constant current driver for HS transmit circuits and to bias other analog circuits, an internal band gap reference circuit and an RREF resistor form the reference current. This circuit requires an external precision resistor (12.0 k Ω± 1 %) connected to the analog ground. 7.6.3 HS detection The ISP1582 handles more than one electrical state, Full-Speed (FS) or High-Speed (HS), under the USB specification. When the USB cable is connected from the peripheral to the host controller, the ISP1582 defaults to the FS state, until it sees a bus reset from the host controller. During the bus reset, the peripheral initiates an HS chirp to detect whether the host controller supports Hi-Speed USB or Original USB. If the HS handshake shows that there is an HS host connected, then the ISP1582 switches to the HS state. In the HS state, the ISP1582 must observe the bus for periodic activity. If the bus remains inactive for 3 ms, the peripheral switches to the FS state to check for a Single-Ended Zero (SE0) condition on the USB bus. If an SE0 condition is detected for the designated time (100 µs to 875 µs; refer to Ref. 1 “Universal Serial Bus Specification Rev. 2.0”, Section 7.1.7.6), the ISP1582 switches to the HS chirp state to perform an HS detection handshake. Otherwise, the ISP1582 remains in the FS state, adhering to the bus-suspend specification. 7.6.4 Isolation Ensure that the DP and DM lines are maintained in a clean state, without any residual voltage or glitches. Once the ISP1582 is reset and the clock is available, ensure that there are no erroneous pulses or glitches even of very small amplitude on the DP and DM lines. Remark: If there are any erroneous unwanted pulses or glitches detected by the ISP1582 DP and DM lines, there is a possibility of the ISP1582 clocking this state into the internal core, causing unknown behaviors. |
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